Basic Language Concepts Describing Design Entities Primary programming abstraction is a design entity

Basic Language Concepts

Describing Design Entities

• Primary programming abstraction is a design entity

• Register, logic block, chip, board, or system

• What aspects of a digital system do we want to describe?

• Interface: how do we connect to it
• Function: what does it do?

• VHDL 1993 vs. VHDL 1987

Describing the Interface: The Entity Construct

• The interface is a collection of ports

• Ports are a new programming object: signal
• Ports have a type, e.g., bit
• Ports have a mode: in, out, inout (bidirectional)

The Signal Object Type

• VHDL supports four basic objects: variables, constants, signals and file types (1993)

• Variable and constant types

• Follow traditional concepts

• The signal object type is motivated by digital system modeling

• Distinct from variable types in the association of time with values
• Implementation of a signal is a sequence of time-value pairs!
• Referred to as the driver for the signal

Example Entity Descriptions

Describing Behavior: The Architecture Construct

• Description of events on output signals in terms of events on input signals: the signal assignment statement

• Specification of propagation delays

• Type bit is not powerful enough for realistic simulation: use the IEEE 1164 value system

Example Entity Descriptions: IEEE 1164

Describing Behavior: The Architecture Construct

• Use of the IEEE 1164 value system requires inclusion of the library and package declaration statements

Libraries and Packages

• Libraries are logical units that are mapped to physical directories

• Packages are repositories for type definitions, procedures, and functions

• User defined vs. system packages

Configurations

• Separate the specification of the interface from that of the implementation

• An entity may have multiple architectures

• Configurations associate an entity with an architecture

• Binding rules: default and explicit

• Use configurations (more later!)

Design Units

• Primary design units

• Entity
• Configuration
• Package Declaration
• These are not dependent on other design units

• Secondary design units

• Package body
• Architecture

• Design units are created in design files

• Now you know the layout of a VHDL program!

Simple Signal Assignment

Simple Signal Assignment Statement

• The constant programming object

• Values cannot be changed

• Use of signals in the architecture

• Internal signals connect components

• A statement is executed when an event takes place on a signal in the RHS of an expression

• 1-1 correspondence between signal assignment statements and signals in the circuit
• Order of statement execution follows propagation of events in the circuit
• Textual order does not imply execution order

Implementation of Signals

Implementation of Signals (cont.)

Implementation of Signals (cont.)

• Driver is set of future signal values: current signal value is provided by the transaction at the head of the list

• We can specify multiple waveform elements in a single assignment statement

• Specifying multiple future values for a signal

• Rules for maintaining the driver

• Conflicting transactions

Example: Waveform Generation

• Multiple waveform elements can be specified in a single signal assignment statement

• Describe the signal transitions at future point in time

• Each transition is specified as a waveform element

Resolved Signal Types

• At any point in time what is the value of the bus signal?

• We need to “resolve” the value

• Take the value at the head of all drivers
• Select one of the values according to a resolution function

• Predefined IEEE 1164 resolved types are std_logic and std_logic_vector

Conditional Signal Assignment

• First true conditional expression determines the output value

Unaffected Signals

• Value of the signal is not changed

• VHDL 1993 only!

Selected Signal Assignment Statement

• The “when others” clause can be used to ensure that all options are covered

• The “unaffected” clause may also be used here

A VHDL Model Template

• library library-name-1, library-name-2;

• use library-name-1.package-name.all;

• use library-name-2.package-name.all;

• entity entity_name is

• port( input signals : in type;

• output signals : out type);

• end entity entity_name;

• architecture arch_name of entity_name is

• -- declare internal signals

• -- you may have multiple signals of different types

• signal internal-signal-1 : type := initialization;

• signal internal-signal-2 : type := initialization;

• begin

• -- specify value of each signal as a function of other signals

• internal-signal-1 <= simple, conditional, or selected CSA;

• internal-signal-2 <= simple, conditional, or selected CSA;

• output-signal-1 <= simple, conditional, or selected CSA;

• output-signal-2 <= simple, conditional, or selected CSA;

• end architecture arch_name;

Delay Models in VHDL

• Inertial delay

• Default delay model
• Suitable for modeling delays through devices such as gates

• Transport Delay

• Model delays through devices with very small inertia, e.g., wires
• All input events are propagated to output signals

• Delta delay

• What about models where no propagation delays are specified?
• Infinitesimally small delay is automatically inserted by the simulator to preserve correct ordering of events

Inertial Delays: Example

• signal <= reject time-expression inertial value-expression after time-expression;

• Most general form of a waveform element

• VHDL 1993 enables specification of pulse rejection width

Transport Delays: Example

Delta Delays: Example

Delta Delays: Behavior

Delay Models: Summary

• Delay models

• Inertial
• For devices with inertia such as gates
• VHDL 1993 supports pulse rejection widths
• Transport
• Ensures propagation of all events
• Typically used to model elements such as wires
• Delta
• Automatically inserted to ensure functional correctness of code blocks that do not specify timing
• Enforces the data dependencies specified in the code

Summary

• Primary unit of abstraction is a design entity

• Design units include

• Primary design units
• entity, configuration, package declaration
• Secondary design units
• architecture, package body

• Concurrent signal assignment statements

• Simple, selected, conditional
• Can be coalesced to form models of combinational circuits