The 40 MHz bunch crossing clock (BC) is generated by DORIC4A using both the leading and trailing edges of the 20 MHz clock generated by the BPM-12s. Therefore if the duty cycle is significantly different from 50%, there will be two “families” of clocks generated, one with a longer and one with a shorter period. This would effectively look like a 40 MHz clock with a high jitter. In order to solve this problem, the BPM-12 has a 5 bit Mark to Space Ratio (MSR) Register which can be used to adjust the duty cycle of the optical 20 MHz signal and hence to minimise the jitter of the recovered 40 MHz BC clock.
The effect of the MSR register on the clock jitter was directly measured by probing the 40 MHz BC clock on a harness test PCB (looking at the output of an LVDS to TTL chip). The results for two doglegs are shown in Figure 1 below.
Figure 1 BPM MSR optimisation using an electrical probe. Module “1” corresponds to the dogleg for module 20220170100029 and module “2” corresponds to 20220170100038.
This method of optimising the jitter can obviously not be used for modules mounted on the barrels and disks. Therefore an alternative optimisation procedure has been developed. The effect of the MSR register on the clock jitter was also determined by using the ROD to measure the duty cycle of the returned signal with the modules in CLOCK/2 mode. The duty cycle was measured by reading out single long events and scanning the RX delay value in 1 ns steps. The duty cycle was measured for different MSR register settings. In order to subtract out asymmetries in the VCSEL on the dogleg or the PIN diode in the BOC, an odd number of “1s” was sent to the BOC command stream in order (by sending a soft reset) to flip the phase of the BPM signal. Then the difference in the duty cycle for the two phases was plotted as a function of MSR register values as shown in Figure 2 and Figure 3 below.
Figure 2 ROD scan to optimise MSR value for module 1. The upper plot shows the measured duty cycle of the returned 20 MHz clock as function of MSR register value, for two phases of the BPM signal. The lower curve shows the difference in the duty cycle between the two phases.
Figure 3 ROD scan to optimise MSR value for module 1. The upper plot shows the measured duty cycle of the returned 20 MHz clock as function of MSR register value, for two phases of the BPM signal. The lower curve shows the difference in the duty cycle between the two phases.
From a linear fit to the plots the optimal values for the MSR registers were 9 and 14 for the two modules. These values are in reasonably good agreement with the direct measurements shown in Figure 1.
Stability of Optimum MSR Value
The stability of the optimum MSR value was studied. Firstly a series of scans were performed over a short period of time, without powering off the VCSELs in the BOC in order to understand the reproducibility of the procedure. The results are summarised in Table 1 below. These results show that the reproducibility of the results is excellent (the standard deviation for the optimal MSR value is 0.14). However the result is significantly different to that obtained from the scan four days previously.
Optimum MSR Value
Table 1 Optimal MSR register values determined from repeated scans. These tests were then repeated with the difference that the VCSEL power was switched off between each scans and the results are summarised in Table 2 below. In this case there is a very much larger spread in optimal MSR values (the standard deviation is 2.6). This is believed to be due to the lasers turning on in different modes, each time they are powered up.
Optimum MSR Value
Table 2 Optimal MSR register values determined from repeated scans, when the BOC VCSELs were not powered off between each scan. The longer term stability was then studied by performing a series of measurements over a period of a few hours for module 29 and the results are given in Table 3 below. The standard deviation of the optimal MSR register values is 0.8 counts. This shows some evidence of drift but it is much smaller than when the BOC VCSELs were powered off between scans. It should be noted that the PIN current on the dogleg was very small for this module, so that the stability might be much worse than for better quality TTC links.
Table 3 Optimal MSR register values determined from repeated scans, when the BOC VCSELs were not powered off between each scan but a delay of 20 minutes between each scan was introduced.
A procedure to optimise the jitter of the BC jitter has been developed using ROD software. By comparisons with direct measurements of the BC jitter it appears to work reasonably well and should be used in ATLAS operation. The stability of this calibration was investigated in order to determine the frequency that it will have to be performed during ATLAS operation. The calibration will certainly have to be done every time the BOC lasers are powered off and on. The question of time variation needs to be investigated with better quality TTC links.