31 August 2016
Faculty of Electrical Engineering, Mathematics and
Computer Architecture for Embedded Systems
Prof.dr.ir. M.J.G. Bekooij
Prof.dr.ir. G.J.M. Smit
V.S. El Hakim, M.Sc.
In the recent years, the radar technology, once used predominantly in the
military, has started to emerge in numerous civilian applications. One of the
areas that this technology appeared is the automotive industry. Nowadays,
we can ﬁnd various radars in modern cars that are used to assist a driver to
ensure a safe drive and increase the quality of the driving experience. The
future of the automotive industry promises to oﬀer a fully autonomous car
which is able to drive itself without any driver assistance. These vehicles will
require powerful radar sensors that can provide precise information about
the surrounding of the vehicle. These sensors will also need a computing
platform that can ensure real-time processing of the received signals.
The subject of this thesis is to investigate the processing platforms for
the real-time signal processing of the automotive FMCW radar developed at
the NXP Semiconductors. The radar sensor is designed to be used in the
The thesis ﬁrst investigates the signal processing algorithm for the MIMO
FMCW radar. It is found that the signal processing consists of the three-
dimensional FFT processing. Taking into account the algorithm and the
real-time requirements of the application, the processing capability of the
Starburst MPSoC, 32 core real-time multiprocessor system developed at the
University of Twente, has been evaluated as a base-band processor for the
signal processing. It was found that the multiprocessor system is not capable
to meet the real-time constraints of the application.
As an alternative processing platform, an FPGA implementation of the
algorithm was proposed and implemented in the Virtex-6 FPGA. The imple-
mentations uses pre-built Xilinx IP cores as hardware components to build
the architecture. The architecture also includes a MicroBlaze core which is
used to generate the artiﬁcial input data for the algorithm and manage the
operation of hardware components through software.
The results of the implementation show that the architecture can provide
reliable outputs regarding the range, velocity and bearing information. The
accuracy of the results are limited by the range, velocity and angular resolu-
the designed waveform pattern. However, the real-time performance on the
architecture cannot be achieved due to the high latencies introduced by the
memory transpose operations. A few techniques have been tested to decrease
the latency bottleneck caused by the SDRAM transpose processes, however
none of them have shown any signiﬁcant improvements.
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