22
CHAPTER 3. REQUIREMENTS
for the computation since it only takes into account the actual computation
required by the FFT algorithm and excludes the overheads such as variable
initializations, function calls, loops and memory accesses. It can be concluded
that the result is 54 times larger than the provided chirp time which is 35.6
µs. Consequently, we can conclude that it is not possible to meet the real
time requirements by using one MicroBlaze core as an FFT processor.
The calculations show that even if we are able to use fixed-point arith-
metic for the FFT process, we are not able to reach the real-time requirement
needed. The MicroBlaze reference guide [13] specifies that the integer addi-
tion and multiplication take 1 clock cycle to finish. By following the same
procedure as above, we can calculate and find that the fixed-point FFT pro-
cess will take at least 48128 clock cycles (481.28 µs) to finish which is 13.5
times bigger than the requirement.
The analysis above shows that using only the Microblaze processors in the
Starburst architecture for base-band processing will not allow to achieve the
real-time requirements demanded by the application. Although, the Star-
bust platform also supports a hardware accelerator integration, the current
application does not benefit from it. Therefore, we should consider alterna-
tive architectures that can provide better performance characteristics. In the
next section we discuss the architecture considerations that can lead to the
higher performance.
3.3
Architecture Considerations
We have seen in Chapter 2 that the three dimensional FFT processing can
give us the range, velocity and the relative position information of the target.
In the previous section, we discussed the computational requirements of the
FFT and found out that using MicroBlaze soft cores for FFT processing
does not allow us to meet the real-time requirements. Consequently, we
concluded that the Starbust architecture is not very useful in terms of meeting
the real-time demands of the radar application. This section discusses the
architecture that can be used to achieve the real-time performance in the
Virtex-6 FPGA.
Implementation of the FMCW signal processing on hardware has been
investigated by number of previous works. In [14], the authors provide an
FPGA based real-time implementation of range-Doppler image processing.
The architecture performs 2D FFT processing by storing the intermediate
data in a DDR SDRAM. The authors propose using two DDR SDRAM
controllers which control the access to two different SDRAM modules. This
prevents any lose of data and allows the data from the second frame to be
3.3. ARCHITECTURE CONSIDERATIONS
23
written to the second SDRAM while the processed data from the first frame
is read from the first SDRAM for the second FFT processing. However, the
authors provide no details about the resource usage and the performance of
the proposed implementation.
In [15], the authors propose an architecture for range-Doppler processing
which supports sampling rates up to 250 MSPS and a maximum of 16 parallel
receiving channels. The architecture uses digital down-sampling to enable
various sampling frequencies to be used and a low pass FIR filter to suppress
the aliasing effects arising from the down-sampling process. Similar to [14],
the data after the first FFT processing is stored in the SDRAM. The authors
propose to interleave the usage of multiple banks of the SDRAM to improve
the data throughput. That is, the outputs of the first FFT block should be
distributed over multiple banks. The paper describes an example addressing
scheme based on that idea which reduces processor stall cycles. In spite of
the fact that the detailed resource usage of the implementation on Virtex-7
FPGA is given, no information on the performance is provided in the paper.
The architecture described in [16] allows a pipelined and parallel hard-
ware implementation of signal processing for an FMCW multichannel radar.
The architecture supports a 3D FFT based signal processing algorithm which
has been described in Chapter 2. It consists of the FFT processing blocks
for range, Doppler and beamforming calculations and the dual-port memory
blocks inserted between them to store the intermediate data. In contrast
to the architectures described above, this implementation does not use the
SDRAM and takes advantage of the FPGA on-chip memory blocks instead.
In addition, the authors provide the hardware resource usage of the archi-
tecture and the processing time of the algorithm implemented on Virtex-5
FPGA.
Another architecture for the radar signal processing is described in [17].
The RF front end of the design has four transmit and four receive antennas
and applies the TDM technique for the transmit signals. This allows sixteen
virtual antennas to be synthesized. Consequently, the processing of the re-
ceived signal is based on the MIMO virtual array concept. The architecture
uses an 1D FFT processing to extract the range information from the ”beat”
signal and a digital beamformer to find the angular information. The imple-
mentation of the architecture is based on combined FPGA and DSP pipeline
approach. The FFT processing is done on the FPGA side, on the other hand
the beamforming algorithm runs on the DSP side. After the processing, the
radar image is displayed on the LCD panel which is actuated by the FPGA
at a frame rate of 50 Hz. According to the authors, the implementation can
achieve a real-time imaging rate of 1.5625 Hz.
To summarize the architectures presented, we can see that there are two