Sequential Circuits A sequential circuit is one whose outputs depend not only on its current inputs, but also on the past sequence of inputs. In other words, sequential circuits must be able to ”remember” (i.e., store) the past history of the inputs in order to produce the present output. The information about the previous inputs history is called the state of the system. A circuit that uses n binary state variables to store its past history can take up to 2n different states. Since n is always finite, sequential circuits are also called finite state machines (FSM).
How can we remember …? The key to build storage circuits is feedback !!
In short, sequential circuits are … circuits consisting of ordinary gates and feedback loops
Two inverters and a feedback loop form a “static” storage cell - The cell will hold value as long as it has power applied
How to get a new value into the storage cell? - selectively break feedback path
- load new value into cell
Latches and Flip-Flops The two most popular varieties of storage cells used to build sequential circuits are: latches and flip-flops. - Latch: level sensitive storage element
- Flip-Flop: edge triggered storage element
Common examples of latches: S-R latch, \S-\R latch, D latch (= gated D latch) Common examples of flip-flops: D-FF, D-FF with enable, Scan-FF, JK-FF, T-FF
S-R (Set-Reset) Latch
S-R latch operation
S-R latch operation (cont’d)
Improper S-R latch operation
State diagram - states: possible values
- transitions: changes based on inputs
Observed R-S latch behavior Very difficult to observe R-S latch in the 1-1 state - one of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0 - a so-called "race condition"
- or non-deterministic transition
S-R Latch timing
S-R Latch
D Latch (= Transparent Latch)
D-Latch Timing Parameters However, violations of setup and hold time still cause metastability
Clock signals Clocks are regular periodic signals used to specify state changes
D Flip-Flop (positive edge triggered)
Timing Behavior of a DFF (positive edge triggered)
Setup and hold times for an edge-triggered DFF
Minimum clock period T ?
Minimum clock period T ? (cont’d)
D Flip-Flop (negative edge triggered)
DFF with asynchronous preset and clear
DFF with asynchronous preset and clear (cont’d)
DFF with enable (cont’d)
Scan DFF
Design for testability: scan chains
JK Flip Flop (rising edge triggered)
Toggle Flip Flop (rising edge triggered)
Activity Design a JK-FF and a T-FF using D-FFs Design a D-FF and a T-FF using JK-FFs Design a D-FF and a JK-FF using T-FFs
Comparison of latches and flip-flops
Comparison of latches and flip-flops (cont’d)
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