Experiment 2



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Işık University Department of Electronics Engineering EE240

Experiment 4

Flip-Flops





  1. Introduction

The circuits stored information about the previous history of inputs are called storage or memory elements. A primitive storage element can be constructed from a small number of gates connecting the outputs back as inputs. These circuits are binary cells capable of storing one bit of information. They have two outputs, one for the normal value and one for the complement value of bit stored in it. Primitive memory elements actually fall into two board classes : latches and flip-flop.

If a latch has only data inputs, it is called an unlocked latch (or only latch). Level-sensitive latches have an additional enable input, sometimes called the clock. Level-sensitive latches continuously sample their inputs when they are enabled. Any change in the level of the input is propagated through to the output. When the enable signal is unasserted, the last value of the inputs is determines the state held by the latch.

Flip-flops differ from latches in that their output change only with repeat to the clock, whereas latches change output when their inputs change. Flip-flops are characterized on the basis of the clock transition that cause the output change : there are positive edge-triggered, negative edge-triggered, and master/slave flip-flops.

A positive edge-triggered flip-flop samples its inputs on the low-to-high clock transition. A negative edge-triggered flip-flop works in a similar fashion, with the input sampled on the high-to-low clock transition.

A master-slave flip-flop is constructed from two stage separate flip-flops. The first stage ( first flip-flop) samples the inputs on the rising edge of a clock signal. The second stage transfer them to the output on the falling edge of the clock signal.

These circuits have two additional control inputs. These are Preset and Clear, which force the output of the flip-flop or latch to the logic-1 or logic-0 state, respectively, independent of the flip-flop or latch inputs [2].
S-R Latch:


  • A S-R ( Set-Reset) latch is the simplest possible memory element.

  • It is constructed by feeding the outputs of two NOR gates back to the other NOR gates input.

  • The inputs R and S are referred to as the Reset and Set inputs, respectively.

  • To understand the operation of the S-R latch consider the following scenarios :

  • S=1 and R=0: The output of the bottom NOR gate is equal to zero, .

  • Hence both inputs to the top NOR gate are equal to zero, thus, .

  • Hence, the input combination S=1 and R=0 leads to the latch being set to .

  • S=0 and R=1: Similar to the arguments above, the outputs become and.

  • We say that the latch is reset.

  • Similary, when the latch is in a reset state ( and ), it will remain there with this input combination.

  • Therefore, with inputs S=0 and R=0, the latch remains in its state.

  • S=1 and R=1: This input combination must be avoided

  • The logic diagram and graphic symbol are shown in Figure.4.1.

  • The following truth table can be summarized the operation of the S-R latch.



(a) Logic Diagram (b)Graphic Symbol




S

R

Q

Q'

Comment

0

0

Q

Q'

Hold State

0

1

0

1

Reset

1

0

1

0

Set

1

1

-

-

Forbidden

(c) Truth table


Figure.4.1 S-R latch with NOR gates.


  • A S-R latch can also be constructed from NAND gates. The graphic symbol, logic diagram, and truth table of the latch are shown in Figure.4.2.


(a) Logic Diagram (b)Graphic Symbol




S

R

Q

Q'

Comment

1

1

Q

Q'

Hold State

0

1

1

0

Set

1

0

0

1

Reset

0

0

-

-

Forbidden

(c) Truth table


Figure.4.2 S-R latch with NAND gates.
Level Sensitive (Clock) S-R Latch:
The operation of the S-R latch can be modified by providing an additional control input that determines when the state of the circuit is to be changed. The logic diagram, graphic symbol, and thruth table of level sensitive S-R latch are shown in Figure.4.3 [1].


(a) Logic Diagram (b)Graphic Symbol




S

R

C

Q

Q'

Comment

0

0

1

Q

Q'

Hold State

0

1

1

0

1

Reset

1

0

1

1

0

Set

1

1

1

-

-

Forbidden

x

x

0

Q

Q'

Hold State

(c) Truth table


Figure.4.3 Level Sensitive S-R latch with NAND gates.

Level Sensitive (Clock) D (Delay) Latch :

One way to eliminate the undesirable condition of the indeterminate state in the S-R latch is to ensure that inputs S and R are never equal to 1 at the state time. This is done level sensitive D latch shown in Figure.4.4. The latch has only two inputs: D and C. The D input connect directly to the S input and its complement is applied to the R input. The D input is sampled when C is equal to 1. If D is equal to 1, the Q output goes to 1. If D is equal to 0, the Q output goes to 0. If C is equal to 0, the Q output remains in its previous state [1].




(a) Logic Diagram (b)Graphic Symbol




C

D

Q

Q'

1

0

0

1

1

1

1

0

0

x

Q

Q'

(c) Truth table


Figure.4.4 Level Sensitive D latch with NAND gates.

Level Sensitive (Clock) J-K Latch:

A level sensitive J-K latch shown in Figure.4.5 is a refinement of the S-R latch in that the indeterminate state of the S-R type is defined in the J-K type. Inputs J and K behave like inputs S and R to set and clear the latch, respectively. The input marked J is for set and the input marked K is for reset. When the both inputs J and K are equal to 1, the latch switches to its complement state, that is , if Q=1, it switches to Q=0, and vice versa. If the C is equal to 0, The output of the latch remains in its previous state [1].


(a) Logic Diagram (b)Graphic Symbol





C

J

K

Q

Q'

Comment

1

0

0

Q

Q'

Hold

1

0

1

0

1

Reset

1

1

0

1

0'

Set

1

1

1

Q'

Q

Toggle

0

x

x

Q

Q'

Hold

(c) Truth table


Figure.4.5 Level Sensitive J-K latch.
D Flip-Flop:


Positive-Edge Triggered:


CLK

D

Q

Q'




0

0

1


1

1

0

0


x

Q

Q'

1


x

Q

Q'

(a) Truth table (b) Graphic Symbol


Figure.4.6. Positive edge-triggered D flip-flop.

Negative-Edge Triggered:



CLK

D

Q

Q'




0

0

1


1

1

0

0


x

Q

Q'

1


x

Q

Q'

(a) Truth table (b) Graphic Symbol


Figure.4.7. Positive edge-triggered D flip-flop.
J-K Flip-Flop:

Positive-Edge Triggered:



CLK

J

K

Q

Q'




0

0

Q

Q'


0

1

0

1




1

0

1

0


1

1

Q'

Q

0

x

x

Q

Q'

1

x

x

Q

Q'

(a) Truth table (b) Graphic Symbol

Figure.4.8. Positive edge-triggered J-K flip-flop.

Negative-Edge Triggered:



CLK

J

K

Q

Q'




0

0

Q

Q'


0

1

0

1




1

0

1

0


1

1

Q'

Q

0

x

x

Q

Q'

1

x

x

Q

Q'

(a) Truth table (b) Graphic Symbol


Figure.4.9. Negative edge-triggered J-K flip-flop.
T Flip-Flop:
The T flip-flop is a single-input version of the J-K flip-flop. As shown in Figure.4.10, the T flip-flop is obtained from the J-k flip-flop when both inputs are tied together. The designation T comes from the ability of the flip-flop to toggle, or complement, its state. While input T is 1, The flip-flop complements its output when the clock pulse occurs. While T is 0, The output of the flip-flop remains in its previous state [1].



CLK

T

Q

Q'




0

Q

Q'


1

Q'

Q

0

x

Q

Q'

1

x

Q

Q'

(a) Truth table (b) Graphic Symbol


Figure.4.10. Negative Edge-Triggered T flip-flop.

  1. Exercises


2.1. Objective
The purpose of this experiment is to investigate the operation of various flip-flop circuits.


2.2. Materials

C.A.D.E.T breadboard

1x74LS00 Quad 2-Input NAND Gate

1x74LS02 Quad 2-Input NOR Gate


1x74LS04 Hex Inverter Gate

1x74LS74 Dual D-Type Positive Edge-Triggered Flip-Flop

1x74LS76 Dual J-K Flip-Flop with Set and Reset

Jumper Wires


2.3. Procedure


  1. Set up the circuit shown in Figure.4.11 using 74LS02 NOR gate.



Figure.4.11 S-R latch with NOR gates.





  1. Wire the power and ground pins to the 74LS02

  2. Connect the inputs S and R to switch1 and switch2, respectively.

  3. Connect the outputs to led1 and led2, respectively.

  4. Fill in the following truth table for this circuit.




Inputs

Outputs

S

R

Q

Q'

0

0







1

0







0

0







1

0







0

1







0

0







1

1







  1. Set up the circuit shown in Figure.4.12 using NAND gate.




Figure.4.12 Level sensitive S-R latch with NAND gates.





  1. Connect the inputs S, R, and C to switch1, switch2, and switch3, respectively.

  2. Connect the outputs to led1 and led2, respectively.

  3. Fill in the following truth table for this circuit.




Inputs

Outputs

C

S

R

Q

Q'

1

0

0







1

1

0







1

0

0







0

1

0







1

1

0







1

0

1







1

0

0







0

1

0










  1. Set up the circuit shown in Figure.4.13 by using NAND and INVERTER gates.


Figure.4.13. Level sensitive D latch.




  1. Connect the inputs D and C to switch1 and switch2, respectively.

  2. Connect the outputs to led1 and led2, respectively.




  1. Fill in the following truth table for this circuit.



Inputs

Outputs

C

D

Q

Q'

1

0







1

1







0

0







1

0







1

1







0

0










  1. Set up the circuit shown in Figure.4.14 by using 74LS74.



PR : Preset( Set)

CL : Clear(Reset)

CLK :Clock

Figure.4.14. Positive edge-triggered D flip-flop.



  1. Connect the D, Preset, and Clear inputs to switch1, switch2, and switch3,

respectively, and the clock input to a push button PB1.

  1. Turn the switch2 and switch3 to logic-1 position.

  2. Connect the outputs of the flip-flop to Led1 and Led2.

  3. Fill in the following table.



Inputs

Outputs

CLK

D

Q

Q'



0









1







0

0






1

1








  1. Turn switch2 to logic-0 position. Switch3 remains in its previous state. Observe the output of the flip-flop and record your observation.

  2. Turn switch2 and switch3 to logic-1 and logic-0 position, respectively. Observe the output of the flip-flop and record your observation.

  3. Set up the circuit shown in Figure.4.15 by using 74LS76.


PR : Preset( Set)

CL : Clear(Reset)

CLK :Clock


Figure.4.15 J-K flip-flop.





  1. Connect the J and K inputs to switch1 and switch2, respectively.

  2. Connect the Preset and Clear inputs to switch3 and switch4, respectively, and the clock input to a push button PB1.

  3. Connect the outputs of the flip-flop to Led1 and Led2.

  4. Turn the switch3 and switch4 to logic-1 position.

  5. Fill in the following table.




Inputs

Outputs

CLK

J

K

Q

Q'



0

0









1

0










0

1









1

1








  1. Turn switch3 to logic-0 position. Switch4 remains in its previous state. Observe the output of the flip-flop and record your observation.

  2. Turn switch3 and switch4 to logic-1 and logic-0 position, respectively. Observe the output of the flip-flop and record your observation.






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