4
CHAPTER 1. INTRODUCTION
radars. These are [6]:
• Ability to measure small ranges with high accuracy
• Ability to measure simultaneously the target range and its relative
velocity
• Signal processing is performed at relatively low frequency ranges, con-
siderably simplifying the realization of the processing circuit
• Functions well in many types of weather and atmospheric conditions
as rain, snow, humidity, fog and dusty conditions
• FMCW modulation is compatible with solid-state transmitters, and
moreover represents the best use of output power available from these
devices
• Small weight and small energy consumption due to absence of high
circuit voltages
The FMCW radar signal processing requires Fast Fourier Transform (FFT)
algorithm to be implemented. More detailed coverage of this topic will be
presented in Chapter 2.
Figure 1.1: FMCW radar block diagram
1.3. RESEARCH PLATFORM
5
1.3
Research Platform
This section introduces the Starburst MPSoC and the hardware platform on
which the radar application will be implemented.
The hardware platform ton which the application will be implemented is
Xilinx’s ML605 development board (Figure 1.2). The board is equipped with
a Virtex-6 FPGA which contains 241,152 logic cells, 37,680 configurable logic
blocks (CLBs) and 416 36 Kb block RAM (BRAM) blocks. Additionally, the
board contains several peripherals such as 512 MB DDR3 SODIMM SDRAM,
an 8-lane PCI Express interface, a tri-mode Ethernet PHY, general purpose
I/O, DVI output and a UART interface [8]. Currently, the platform is used
for the development and testing of the Starburst MPSoC.
Figure 1.2: Xilinx ML605 development board
The Starburst MPSoC consists of number of processing tiles connected
through Network on Chip. Currently, the platform supports up to 32 pro-
cessing cores and a Linux core to provide an easy interaction with a host PC.
In addition, the platform also supports hardware accelerator integration.
The main processing tile of the Starburst is a MicroBlaze, the soft proces-
sor core developed by Xilinx. The MicroBlaze is highly configurable soft-core
processor that can be implemented using FPGA logic. It is based on Harvard
CPU architecture and has a 5 stage single issue instruction pipeline. It has
additional hardware support for number of operations such as floating point
processing, division, multiplication and bit shifting. In addition, MicroBlaze
6
CHAPTER 1. INTRODUCTION
has a local memory and a scratchpad memory which sizes are reconfigurable
at design time. Both memories are connected to MicroBlaze through Local
Memory Bus (LMB), and can be accessed from local MicroBlaze core, al-
though, the scratchpad memory is also connected to the ring interconnect
and can accept data from it. All the processors run a real-time POSIX com-
patible micro-kernel called Helix which supports the newlib C library and
implements the Pthread standard.
The communication network of Starburst consists of two parts. The first
one is the Nebula ring interconnect which supports all to all communication
between processing tiles and hardware accelerators. The ring is unidirec-
tional and has an arbitration policy based on ring slotting which prevents
the occurrence of starvation. Each processing tile is connected to a router
via a Network Interface and each router is connected to its two neighbouring
routers which makes a ring-like structure. The processors are processing the
stream of data and can transfer their computation results to other processors
connected to the ring. The communication between processors is achieved
through C-FIFO algorithm which allows arbitrary number of simultaneous
streams between processor tiles. The second communication network is the
Warpfield arbitration tree which provides a communication to the shared
resources such as UART, DVI and SDRAM. The access to the resources is
given on a first-come-first-served basis.
The Starburst MPSoC allows a number of CPUs to run in parallel to
achieve a high computation power. Additional support of hardware accel-
erators allows to improve the performance for the applications which are
limited by the computational power of MicroBlaze cores. The resulting het-
erogeneous MPSoC is an important research and development platform for
the stream processing applications which also allows real-time multiprocessor
system analysis [4].
1.4
Problem Description
Recent developments in the digital electronics has led to the major improve-
ments in number of areas.
Novel microwave transmitters are capable of
generating extremely high frequency signals in real time which allows the
usage of these high frequency signals in numerous applications. Recently,
number of automotive radar chips have emerged which take advantage of the
mm-Wave band such as 77 Ghz and 79 Ghz [3].
Earlier this year, NXP Semiconductors introduced it’s 77 GHz single-chip
radar transceiver (Figure 1.3) which is based on multiple-input multiple-
output (MIMO) FMCW principle. The chip is planned to be used in self-
1.4. PROBLEM DESCRIPTION
7
driving vehicles such as self-driving cars.
Currently, researchers at NXP
Semiconductors are working on the development of the base-band processor
for the above mentioned chip.
Figure 1.3: NXP Semiconductor’s automotive radar chip
This thesis works as a supportive research to test concepts of the Starburst
MPSoC to be used in a base-band processor. The main aim of this research
is to analyse the computational and real-time requirements of the FMCW
radar application and extend the Starbust MPSoC platform accordingly to
support the MIMO FMCW radar signal processing.
The main research objectives for the thesis are:
• Research the theory of the MIMO FMCW radar signal processing and
evaluate the proposed signal processing architectures.
• Propose the efficient architecture for the Starburst platform to support
the FMCW radar application.
• Propose and implement a new architecture in case Starburst cannot
achieve the real-time computational requirements for the application.