All-optical lip-lops based on semiconductor technologies
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carry out binary modulo-2 addition and store the current state of the counter; whereas the
AND gate is used to generate carry pulse when a clock pulse injects into a stage that has
already been in “state 1”. Different from the schemes proposed in (Poustie et al., 2000;
Benner et al., 1990; Feuerstein et al., 1991), whose bit storage is implemented by fiber loop
memory and has a fixed counting speed determined by the fiber length, the counter shown
in Fig. 22 utilizes SR latches to memorize its current state, and can work at different
counting speeds without the necessity of any reconfiguration or re-synchronization.
(a)
(b)
(c)
(d)
Fig. 23. All-optical two-bit binary counting at three different speeds: (a) 40 kHz; (b) 80 kHz;
(c) 120 kHz. (d): transition time of SR latch
Referring to (Wang et al., 2009, b) for all the details of the experiment, Fig. 23 demonstrates
that the counter can work at three different counting speeds, 40 kHz, 80 kHz, and 120 kHz
without any reconfiguration. It is observed that each time a clock pulse comes, Q
2
Q
1
adds 1,
from 00 to 01, 10, 11, and finally returns to 00, and when Q
i
(i=1,2) changes from 1 to 0 a
carry pulse is generated, having a good agreement with Fig. 22 (b). Q
1
and “Carry 1” have a
repetition rate 1/2 of the clock; whereas Q
2
and “Carry 2” have a repetition rate 1/4 of the
clock. The counter can therefore be used as an all-optical frequency divider.
In principle, by cascading n counter stages it is possible to demonstrate n-bit binary counter
which can count from 0 to 2
n
-1. However, the cascadability of this scheme is limited by the
signal degradation of carry pulses, which mainly comes from the accumulated ASE noise of
SOA. To evaluate the signal degradation of carry pulses quantitatively, Q-factor
measurement has been carried out. The Q-factors of Q
1
and Q
2
are 16.1 and 19.9 respectively,
only determined by the properties of two latches. The Q-factor of “Carry 1” is 17.0, while
exploiting an ASE pedestal suppression technique, we obtained “Carry 2” pulse with Q-
factor of 15.0, only slightly lower than “Carry 1”. These values confirm the good
cascadability of this scheme.
In the experiment the operation speed is limited to hundreds of kHz. Since the AND gates
are all based on nonlinear effects in the SOA, which have very fast dynamics, the operation
speed limitation is mainly due to the switching-on of the SR latch, reported also in Fig. 23
(d). This time depends on the cavity length of fiber ring lasers, and in our setup each ring is
about 40m due to the discrete fiber pigtailed implementation. Again, photonic integration is
a feasible solution to reduce the cavity length to the range of millimeters, shortening the
transition time to <100 ps, and making GHz operation speed possible.
6. Ultra-fast SOA-based all-optical flip-flop
An all-optical flip-flop based on two coupled ring lasers presents a fast falling edge (as fast
as the input pulse rising edge), but a slow rising edge (several round-trip times), which
mainly limits the flip-flop operating speed for optical packet switching. In this paragraph,
using two SOA-based optical NOT logic gates and two identical slow flip-flops, we obtain
an optical flip-flop with ultra-fast transition times for both rising and falling edges
(Malacarne et al., 2008). The experimental setup is shown in Fig. 24, while the operating
principle is described in Fig. 25. Flip-flop 1 is controlled by reset and assistant pulses
whereas flip-flop 2 is controlled by assistant and set pulses. Exploiting a 10GHz pattern
generator we produce a 16ps-edge pulsed sequence with a pulse-width of 1µs and a
repetition rate of 50KHz. Such a wide pulse has been set in order to maintain the gain
saturation level into the ring laser to be quenched for several round trip time, allowing to
reach a lasing steady condition. The reset pulse is delayed by 10µs (T
d1
) with respect to the
set pulse whereas the assistant pulse is delayed by 15µs (T
d1
+T
d2
) with respect to the set
pulse. As shown in Fig. 25, a set pulse is firstly injected into ring 3 switching off signal B.
Secondly, a reset pulse is injected into ring 1 switching off signal A. Then two assistant
pulses are injected into ring 2 and ring 4 simultaneously. They switch off ring 2 and ring 4,
switching on ring 1 and ring 3 respectively. Consequently, signals A and B are switched on
at the same time. As pointed out above, both signals A and B have a fast falling edge, but a
slow rising edge. Exploiting the optical NOT logic gate 1, signal A is inverted in order to
obtain signal C, which therefore presents a fast rising edge and a slow falling edge. Since
signals A and B are switched on by two assistant pulses simultaneously, the slow falling
edge of signal C is almost synchronized with the slow rising edge of signal B, and when they
are added together, the slow edges compensate each other in terms of intensity profile. This
way, signal D (the sum of signals B and C) has a fast rising edge due to signal C and a fast
falling edge coming from signal B. The wavelengths of signals A, B and C are 1550nm,
1558.2nm and 1557.4nm respectively, thus signal D is made of two different wavelengths, as
highlighted in Fig. 24, and a tunable filter with -3dB bandwidth of 4.5nm is used to filter and
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