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LEON/GRLIB Guide
2
System Design Guidelines
2.1
Introduction
The design and partitioning of a system strongly depends on the intended use for the system. The sec-
tions below make general recommendations based on the components available in GRLIB.
2.2
Minimal System
A minimal LEON/GRLIB system consists of the following IP cores:
TABLE 1. Minimal LEON system
Core
Description
CLKGEN
Clock generator
RSTGEN
Reset generator. Generating a glitch free on-chip system reset signal.
AHBCTRL
AHB arbiter/controller.
APBCTRL
AHB/APB bridge/controller. Must be included
in order to interface
peripheral cores such as interrupt controller and timer unit.
LEON3/4
LEON3/4 processor
IRQMP
Interrupt controller
GPTIMER
General Purpose Timer Unit
MEMCTRL
Memory controller providing access to (P)ROM and RAM. The
GRLIB IP Library contains several memory controllers. It is also possi-
ble to include on-chip ROM and RAM by using the AHBROM and
AHBRAM IP cores.
In addition to the cores described above it is recommended to include a LEON Debug Support Unit
(DSU) and a debug communication link to be able to control the processor and inspect the system via
the GRMON Debug Monitor. GRLIB contains several debug communication link (DCL) cores. All
DCL cores are controlled over an external link to make accesses on an on-chip AHB bus. Examples of
DCL cores are the AHBJTAG, AHBUART and USBDCL cores. See section 5 for more information.
In order for the processor to be able to communicate with the outside world, an 8-bit UART and a
General Purpose I/O port is also typically included in a LEON design.
With the above considerations the recommended minimal LEON/GRLIB system also includes the
following cores:
TABLE 2. Additional recommended cores for minimal LEON system
Core
Description
DSU3/4
LEON Debug Support Unit
AHBJTAG/
AHBUART/
USBDCL/
GRETH
Debug communication link. AHBJTAG
provides an external JTAG
link. Other examples include AHBUART (serial UART), USBDCL
(USB), GRETH (Ethernet debug communication link is available as
part of Ethernet MAC core).
APBUART
8-bit UART
GRGPIO
General Purpose I/O Port
2.3
Memory Map
2.3.1 Overview
Most LEON systems use a memory map where ROM (boot PROM) is mapped at address
0x00000000 and RAM is mapped at address 0x40000000. Traditionally the AHB/APB bridge has
been mapped at 0x80000000 and peripherals such as timer, interrupt controller and UART have been
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LEON/GRLIB Guide
placed at fixed offsets in the APB address space. Table 3 shows the base addresses historically used in
LEON systems.
TABLE 3. Peripheral base addresses, legacy systems
Base address
Description
0x80000000
LEON2 memory controller
0x80000100
Generic UART (APBUART)
0x80000200
Multi-processor interrupt controller (IRQMP)
0x80000300
Modular timer unit (GPTIMER)
Some software may not read all peripheral core base addresses from plug&play and instead assume
that some peripherals are mapped at these fixed offsets. One of the affected software packages is the
BCC toolchain, where the -qambapp switch must be given in order for the produced software to find
the UART, timer and interrupt controller in case these peripherals are not mapped at the addresses
given in table 3.
The traditional memory map described above does not fit all systems. In particular one or several
large memory area (>= 1 GiB) may be difficult to place as the standard AHB decoder in GRLIB con-
strains the base address of a memory area based on the memory area size. Other reasons include that
the use of AHB-to-AHB bridges that limit how the memory areas can be arranged. As a result of this,
there are several LEON/GRLIB designs with different memory maps. In order to ease software devel-
opment, this document contains some recommendations on how memory maps should be arranged.
Section 2.3.2 shows a traditional LEON/GRLIB memory map and section 2.3.3 contains recommen-
dations on how to arrange memory maps that contains large memory areas.
2.3.2 Typical LEON/GRLIB Memory Map
In order to use toolchains and other software distributed by Cobham Gaisler, some constraints in the
system’s memory map should be observed. A typical LEON3 system has the following memory map:
TABLE 4. Typical LEON3 memory map
Base address
Description
0x00000000
PROM
0x40000000
RAM base address. Some systems place SRAM at address 0x40000000
and SDRAM at base address 0x60000000. When SRAM is disabled the
memory controller may automatically adjust the SDRAM base address
to 0x40000000.
0x80000000
Base address of first AHB/APB bridge connecting interrupt controller,
UART(s) and timer unit.
0x90000000
Debug Support Unit register interface
0xFFF00000
AHB I/O area (if used by any core)
0xFFFFF000
Plug’n’play area (always located within AHB I/O area)
The most important areas in the table above are base addresses for ROM and RAM. The default linker
scripts make assumptions on the locations of these areas. Also, software that makes use of the GRLIB
AMBA plug’n’play areas often assume the main plug’n’play area to be located at 0xFFFFF000. The
information in this area is used by software to dynamically find the addresses of all peripherals in the
system.
The location of the first AHB/APB bridge (0x80000000 in the table above) is generally of less impor-
tance. Some legacy software may assume that the bridge is located at the specified address.
The typical memory map given above constrains the maximum size of a memory area in the design.
The GRLIB infrastructure requires that memory areas are binary aligned according to their size. This
means that a 2 GiB memory area must start on address 0x00000000 or address 0x80000000. In order