Power electronics digital notes b. Tech III year

parallel inverter
. 
The operation of this inverter can be explained in the following modes.
Mode I 
In this mode, 
SCR
T1 is conducting and a current flow in the upper half of primary 
winding. 
SCR
T2 is OFF. As a result an emf Vs is induced across upper as well as lower half of 
the primary winding. 
In other words total voltage across primary winding is 2 Vs. Now the capacitor C charges to a 
voltage of 2Vs with upper plate as positive. 
 
Figure: 5.13 Circuit diagram of parallel inverter
 
 
 

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Mode II 
At time to, T2 is turned ON by applying a trigger pulse to its gate. At this time t=0, capacitor 
voltage 2Vs appears as a reverse bias across T1, it is therefore turned OFF. A current Io begins 
to flow through T2 and lower half of primary winding. Now the capacitor has charged (upper 
plate as negative) from +2Vs to -2Vs at time t=t1. Load voltage also changes from Vs at t=0 to 
–
Vs at t=t1. 
Mode III 
When capacitor has charged to 
–
Vs, T1 may be tuned ON at any time When T1 is triggered, 
capacitor voltage 2Vs applies a reverse bias across T2, it is therefore turned OFF. After T2 is 
OFF, capacitor starts discharging, and charged to the opposite direction, the upper plate as 
positive. 
Paralleled Commutated Inverter 
Fig 1: is a schematic of the classical 
parallel 
commutated square wave inverter bridge. It is 
being included here for illustrative purposes since most other circuits utilize this circuit or a 
variation there of. The waveform generated and supplied to the load is basically a square wave 
having a peak to peak amplitude of twice the DC supply voltage and a period that is determined 
by the relate at which