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Fig. 21. Experimental setup of three-state all-optical memory
The experiments has shown an “on-off” extinction ratio of 40 dB for each state. The required
switching energy is in the order of 12 to 19nJ, depending on the wavelength chosen for the
set pulses. In the exploited set-up the ring length of the three cavities is about 42m, giving a
rise time of about 210ns, while falling time can be as low as 20ps. Of course, photonic
integration will reduce the rise time down to 40ps as well, making GHz switching possible.
By coupling N ring lasers, the scheme could be scaled up to N-state, in which output light of
one SOA saturates N-1 other SOAs, requiring higher optical power for stable flip-flop
operation. Moreover, N(N-1)/2 couplers would be used to couple N ring lasers together and
the cavity length would also be increased. Photonic integration or hybrid integration would
be useful to reduce both the cavity loss and the cavity length; and make high optical power
and fast switching speed possible.
5. Latch-based all-optical counter
An extremely interesting and promising application of clocked flip-flops is the all-optical
counter. As a key component in both areas of optical computing and communication, all-
optical binary counter can be used as a finite-state machine in optical computing and can
also be used for header recognizing and payload processing in optical packet switching
networks. Nevertheless, there are few papers related to all-optical counter (Poustie et al.,
2000; Benner et al., 1990; Feuerstein et al., 1991). In (Poustie et al., 2000) an all-optical binary
counter based on terahertz optical asymmetric demultiplexer (TOAD) switching gate was
demonstrated, which is however not integrable due to the nonlinear fiber loop mirrors in
the TOADs. In (Benner et al., 1990; Feuerstein et al., 1991) a counter is presented but it
requires optical-to-electrical conversion in the coupler switches. Furthermore, in these
reported schemes, due to the lack of optical latch or other memory element, the storage of
optical bit is realized by fiber loop memory, which requires precise synchronization of the
arrival time of optical pulses and makes the counting speed fixed, depending on the fiber
length in the loop memory.
Extending the setup of the above mentioned T flip-flop, we have demonstrated the first SR
latch based all-optical binary counter (Wang et al., 2009,b), which is able to work at different
counting speeds without the necessity of any reconfiguration or re-synchronization. The SR
latch is used for optical bit storage, to memorize the accumulated number of input pulses
and to carry out binary modulo-2 addition between the accumulated number and new input
pulses. The AND logic gate is used for binary carry signal generation when the input and
stored bit are both “1”. We also presented two-bit binary counting operation as well as 1/2
and 1/4 all-optical frequency division at different frequencies, and Q-factor measurement is
performed to evaluate the signal degradation and confirm the cascadability of the scheme.
Finally, the operation speed limitation of clocked flip-flop and the counter is investigated
.
The setup of optical counter is shown in Fig. 22 (a), which consists of two cascaded stages.
Carry 1 signal from stage 1 is used as the input of stage 2. The latches’ output, Q
2
Q
1
,
represent the output of the counter.
Q
1
CLK
∩Q
1
90/10
50/50
CLK
BPF
BPF
Carry 1
delay
90/10
Flip-Flop 1
Set
1
Reset
1
Q
2
90/10
50/50
BPF
BPF
delay
90/10
Flip-Flop 2
Set
2
Reset
2
Carry 1
∩Q
2
Carry 2
CLK
Set
1
Reset
1
Carry
1
Q
1
AND 1
CLK
∩Q1
0
0
1
1
0
Set
2
Reset
2
Carry
2
Q
2
0
0
1
1
0
AND 2
Carry 1
∩Q
2
Q
2
Q
1
00 01 10 11 00
(a)
(b)
Fig. 22. All-optical binary counter: (a) logic circuits; (b) working principle.
The working principle of the counter is shown in Fig. 22 (b). At first, both latch 1 and latch 2
are in “state 0”, Q
2
Q
1
=00. When the first clock pulse comes, it injects into “Set
1
” directly, but
since Q
1
=0, it can not pass through “AND 1”, so only “Set
1
” receives a pulse and latch 1 is
set to “state 1”, Q
2
Q
1
=01. When the 2
nd
clock pulse comes, since Q
1
=1 it can pass through
“AND 1” and reach both “Set
1
” and “Reset
1
” ports. However, due to the fiber delay line,
“Reset
1
” receives the pulse later than “Set
1
”, so latch 1 is then set to “state 0”. The output
pulse of “AND 1” is used as “Carry 1” and is injected into stage 2. Since Q2=0, “Carry 1”
pulse can not pass through “AND 2”, so only “Set
2
” receives the pulse and latch 2 is set to
“state 1”. Now we have Q
2
Q
1
=10. When the third pulse comes, it is blocked by “AND 1”
since Q1=0, so latch 1 is set to “state 1”, Q
2
Q
1
=11. Finally, when the 4
th
pulse comes, since
Q
1
=1 it can pass through “AND 1” and reach “Reset
1
”. Due to the fiber delay, “Reset1”
receives a pulse later so latch 1 is set to “state 0”. Then the output “Carry 1” pulse from
“AND 1” injects into stage 2, passes through “AND 2” and sets latch 2 to “state 0”. Now the
counter returns to the initial state, Q
2
Q
1
=00, and the “Carry 2” pulse from “AND 2” can be
used as the input of next stage. In each stage, the SR latch is used as a memory element to
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