Figure 1. Timing
diagram for CPUCLK, HCLK and HCLKEN
CPUCLK
HCLK
HCLKEN
CPUCLK
HCLK
HCLKEN
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4.3.4 Multicycle Paths
Paths going through both CPU and AHB clock domains have propagation time of one AHB clock
cycle, and should be marked as multicycle paths with following exceptions:
Start point
Through
End point
Propagation time
leon3s2x core
CPUCLK
ahbi
CPUCLK
N CPUCLK
CPUCLK
ahbsi
CPUCLK
N CPUCLK
CPUCLK
ahbso
CPUCLK
N CPUCLK
HCLK
irqi
CPUCLK
1 CPUCLK
CPUCLK
irqo
HCLK
1 CPUCLK
CPUCLK
u0_0/p0/c0/sync0/r[*]
(register)
1 CPUCLK
dsu3_2x core
CPUCLK
ahbmi
CPUCLK
N CPUCLK
CPUCLK
ahbsi
CPUCLK
N CPUCLK
dsui
CPUCLK
1 CPUCLK
r[*] (register)
rh[*] (register)
1 CPUCLK
irqmp2x core
r2[*] (register)
r[*] (register)
1 CPUCLK
* N is ratio between CPU and AHB clock frequency (2, 3, ...)
Sample DC script defining multicycle paths and exceptions is provided in the design directory
(dblclk.dc).
Figure 2 shows synchronization of AHB signals starting in HCLK clock domain and ending in CPU-
CLK domain (inside the double clocked cores LEON3S2X and DSU3_2X). These AHB signals are
captured by registers in CPUCLK domain at the end of AHB clock cycle, allowing propagation time
of 2 or more CPUCLK cycles (one HCLK cycle). The end of the AHB clock cycle is indicated by the
AHB clock qualifier signal HCLKEN. One of the inputs of the AND gate in figure below is connected
to the clock qualifier signal HCLKEN ensuring that the value of the signal AHBI is latched into R2 at
the end of AHB cycle (HCLKEN = ‘1’). The value of signal AHBI is not valid in the CPUCLK clock
domain if the qualifier signal HCLKEN is low. In this case, the AND gate will be closed and the value
of the signal AHBI will not propagate to register R2.
Figure 2. Synchronization between HCLK and CPUCLK clock domains
CPUCLK
HCLK
HCLKEN
D
Q
D
Q
HCLK
D
Q
AHBI
CPUCLK
CPUCLK
Clock Domain
Clock Domain
R1
R2
LEON3S2X
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Synchronization of AHB signals going from the double clocked cores to the AHB clock domain is
shown if figure 3. The AND gate is open when CPU (or DSU) performs an AHB access (AHBEN =
‘1’). When the AND gate is open, the signal AHBO will be stable during the whole AHB cycle and its
value propagates to the HCLK clock domain (AHB bus). When CPU does not perform AHB access
(CLKEN = ‘1’) the AND gate is closed (AHBEN = ‘0’) disabling propagation of signal AHBO to the
HCLK clock domain.
Figure 3. Synchronization between CPUCLK and HCLK clock domains
HCLK
CPUCLK
AHBEN
D
Q
D
Q
CPUCLK
D
Q
AHBO
HCLK
HCLK
Clock Domain
Clock Domain
R1
R2
LEON3S2X
The AND gates in figures 2 and 3 are 2-input clock AND gates. Synthesis tool should not optimize
these AND gates. Sample DC-script puts ‘don’t-touch’ attribute on these cells to prevent optimiza-
tion.
The multicycle constraints for the GRLIB double clocked cores are typically defined by start clock
domain, intermediate points and end clock domain. Although FPGA synthesis tools provide support
for multicycle paths, they do not provide or have limited support for this type of multicycle con-
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straints (start clock domain, intermediate points, end clock domain). This limitation results in over-
constrained FPGA designs (multicycle paths become single cycle) which are fully functional and suit-
able for FPGA prototyping.
4.3.5 Dynamic Clock Switching
An optional clock multiplexer switching between the CPU and AHB clocks and providing clock for
double-clocked cores can be enabled. The clock multiplexer is used to dynamically change frequency
of the CPU core, e.g. CPU can run at lower AHB frequency during periods with low CPU load and at
twice the AHB frequency during periods with high CPU load.
The clock switching is controlled by writing to the qmod modules APB register (default address
0x80000400), bit 0: writing ‘1’ will switch to the CPU clock and writing ‘0’ will switch to the AHB
clock.
The clock multiplexer is glitch-free, during clock switching the deselected clock is turned-off (gated)
before the selected clock is enabled and selected.
Dynamic clock switching is available for Xilinx and generic technologies.
4.3.6 Configuration
xconfig
Clock ratios 2x, 3x and 4x between CPU and AHB clock are supported. Clock ratio 2x is supported
for all technologies, ratios 3x and 4x are supported for ASIC technologies. Dynamic clock switching
is available for Xilinx and ASIC technologies.
leon3s2x
Double-clocked LEON3 core is configured similarly to standard LEON3 core (leon3s) through
VHDL generics. An additional VHDL generic clk2x is set to ((clock ratio - 1) + (8 * dyn)) where dyn
is 1 if dynamic clock switching is enabled and 0 if disabled.
qmod
Local qmod module generates AHB clock qualifier signal and optionally controls dynamic clock
switching. The module is configured through VHDL - generics defining clock ratio (clkfact), dynamic
clock switching (dynfreq) and address mapping of modules APB register (pindex, paddr, pmask).
irqmp_2x
VHDL generic clkfact should be set to clock ratio between CPU and AHB clocks.
4.4
Clock gating
4.4.1 Overview
GRLIB contains support for using clock gating for both the processors and peripheral IP cores. The
GRCLKGATE unit described in the GRLIB IP Core User’s Manual can be used both to gate peripher-
als and to provide automatic processor (and floating-point unit) clock gating.
4.4.2 LEON clock gating
To further reduce the power consumption of the processor, the clock can be gated-off when the pro-
cessor has entered power-down state. Since the cache controllers and MMU operate in parallel with
the processor, the clock cannot be gated immediately when the processor has entered the power-down
state. Instead, a power-down signal (DBGO.idle) is generated when all outstanding AHB accesses
have been completed and it is safe to gate the clock. This signal should be clocked though a positive-
edge flip-flop followed by a negative-edge flip-flop to guarantee that the clock is gated off during the
clock-low phase. To ensure proper start-up state, the clock should not be gated during reset and at
least 3 clocks after that reset has been de-asserted.