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id => id,
atmi => atmi(0),
atmo => atmo(0));
-- Here other tasks can be performed
at_write_32_nb_fin(
id => id,
wait_for_op => true,
screenoutput => false,
ready => ready,
atmi => atmi(0),
atmo => atmo(0));
The first call initiates a write access to address 0x40000000 with data 0x01234567. The access should
start immediately, not assert HLOCK and use the specified HPROT (0b0011). The first call will
assign an access identifier to the variable id. This identifier is used by AT_AHB_MST to keep track of
the access. The same access identifier must then be used in the call to at_write_32_nb_fin(..). The
core will try to perform the write access even if the call to at_write_32_nb_fin(..) never takes place.
However, if at_write_32_nb_fin(..) is never called, the core will keep a record of the completed
access in its internal data structures forever.
A call to at___nb_fin(..) procedure will block if the wait_for_op parameter is set
to true. If wait_for_op is set to false, the call will return immediately and the ready variable must be
checked to see if AT_AHB_MST completed the access.
The description given for write operations above also applies to read operations. Note that for non-
blocking reads (at_read__nb(..) / at_read__nb_fin(..)), the data will be returned when
at_read__nb_fin(..) is called. The first call only tells the master to initiate an access, the
at_read__nb_fin(..) call will tell you when, and if, the access has completed and the master
will have data available.
As mentioned above, the core can also generate burst accesses. In the case of non-blocking burst
accesses, the id and ready parameters will be arrays instead of single values.
The description above covers basic operation of AT_AHB_MST. Please refer to the grlib.at_ahb_m-
st_pkg package located at lib/grlib/atf/at_ahb_mst_pkg.vhd to see all available procedure calls. Each
call and its parameters are documented in the package.
7.3
AT AHB Slave
7.3.1 Description
The AT AHB Slave (AT_AHB_SLV) is an non-synthesizable AHB slave core with a debug interface
that allows insertion of custom AHB replies and access to the core’s internal memory structures.
7.3.2 Initialization and Instantiation
The component for the slave is defined in the package grlib.at_pkg and the procedure calls used to
access the slave via its debug interface are available in the package grlib.at_ahb_slv_pkg. In order to
instantiate the slave, the following libraries should be included:
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.at_pkg.all;
use grlib.at_ahb_slv_pkg.all;
The component for AT_AHB_SLV has the following interface:
component at_ahb_slv is
generic (
hindex : integer := 0; -- Slave index
bank0addr : integer := 0;
bank0mask : integer := 0;
bank0type : integer := 0; -- 0: memory area 1: I/O area
bank0cache : integer := 0; -- Cachable
bank0prefetch : integer := 0; -- Prefetchable
bank0ws : integer := 0; -- Waitstates
bank0rws : integer := 0; -- Random wait states 'ws' is the maxmimum
bank0dataload : integer := 0; -- Load data from file
bank0datafile : string := "none"; -- Initial data for bank
bank1addr : integer := 0;
bank1mask : integer := 0;
bank1type : integer := 0; -- 0: memory area 1: I/O area
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bank1cache : integer := 0; -- Cachable
bank1prefetch : integer := 0; -- Prefetchable
bank1ws : integer := 0; -- Waitstates
bank1rws : integer := 0; -- Random wait states 'ws' is the maxmimum
bank1dataload : integer := 0; -- Load data from file
bank1datafile : string := "none"; -- Initial data for bank
bank2addr : integer := 0;
bank2mask : integer := 0;
bank2type : integer := 0; -- 0: memory area 1: I/O area
bank2cache : integer := 0; -- Cachable
bank2prefetch : integer := 0; -- Prefetchable
bank2ws : integer := 0; -- Waitstates
bank2rws : integer := 0; -- Random wait states 'ws' is the maxmimum
bank2dataload : integer := 0; -- Load data from file
bank2datafile : string := "none"; -- Initial data for bank
bank3addr : integer := 0;
bank3mask : integer := 0;
bank3type : integer := 0; -- 0: memory area 1: I/O area
bank3cache : integer := 0; -- Cachable
bank3prefetch : integer := 0; -- Prefetchable
bank3ws : integer := 0; -- Waitstates
bank3rws : integer := 0; -- Random wait states 'ws' is the maxmimum
bank3dataload : integer := 0; -- Load data from file
bank3datafile : string := "none"; -- Initial data for bank
grlibdatamux : integer := 1 -- GRLIB AMBA data MUX:ing
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in at_slv_dbg_in_type;
dbgo : out at_slv_dbg_out_type
);
end component;
The
hindex generic must match the bus index in the same way as for other GRLIB cores. The
grlib-
datamux generic decides if the core should use AMBA compliant data multiplexing (
grlibdatamux =>
0) or the simplified data multiplexing scheme (grlibdatamux => 1) used in GRLIB (see the GRLIB IP
Library User’s Manual,
grlib.pdf, for details).
For use in a normal GRLIB system, the default value is recommended. The other generics define the
size and behavior of the, up to, four available AHB memory areas (banks). Each bank is configured
via a set of generics described in the table below:
TABLE 11. AT_AHB_SLV VHDL generics
VHDL generic
Description
bank*addr
Bank base address. Set in the same manner as for all GRLIB AHB slaves
bank*mask
Bank mask. Decides how many of the bank*addr bits that are matched against the
incoming AMBA HADDR and thereby also determines the size of the memory area.
bank*type
Selects if the bank is an AHB memory area or an AHB I/O area. The AT_AHB_SLV
package defines to constants that can be used to select the type: AT_AHBSLV_MEM
and AT_AHBSLV_IO.
bank*cache
Determines if bank is cacheable. This value is only used when banktype is set to
AT_AHBSLV_MEM.
bank*prefetch
Determines if the bank is prefetchable. This value is only used when banktype is set
to AT_AHBSLV_MEM.
bank*ws
Number of wait states that the core will insert on each access to the bank.
bank*rws
Enables random wait states. If this generic is set to AT_AHBSLV_RANDOM_WS,
the core will insert between 0 and bank*ws wait states on each access. If this generic
is set to AT_AHBSLV_FIXED_WS the core will always insert bank*ws wait states.
bank*dataload
If this generics is non-zero, the core will load initial memory data from the SREC file
specified by bank*datafile.
bank*datafile
See above.