Aims: This module introduces you to the design and implementation of digital circuits. Topics include: combinational and sequential circuit analysis and design, digital circuit design optimization methods using random logic gates, multiplexers, decoders, registers, counters and programmable logic arrays. Laboratory experiments will be used to reinforce the theoretical concepts discussed in lectures. The lab experiments will involve the design and implementation of digital circuits. Emphasis is on the use computer aided tools in the design, simulation, and testing of digital circuits.
Teaching Methods: 41 hours Lectures (2-3 per week) + 4 hours Tutorials (1 per 3 weeks) + 3 hours Laboratory (1 per 4 weeks)
A student completing this module should be able to:
Define the problem (Inputs and Outputs), write its functions. (A, B, C)
Minimize functions using any type of minimizing algorithms (Boolean Algebra, Karnaugh map or Tabulation Method). (A, B)
Implement functions using digital circuit (Combinational or Sequential). (A, B)
Have knowledge in analyzing and designing procedures of Combinational and Sequential circuits. (B, C)
Have knowledge in designing and analyzing circuits with Flip-Flops, Counters and Registers. (B, C)
Work effectively with others. (D)
Use simulation software, for testing the designed circuit. (C, D)
Learning outcomes (1), (2), and (3) are assessed by examinations, tutorial and in the laboratory. Learning outcomes (4), (5), and (6) is assessed by course work/workshops. Learning outcomes (7) is assessed in the laboratory.
Contribution to Programme Learning Outcomes:
A1, A3, A5, B1, B3, C6, D3, D6
Synopsis: Introduction to Digital logic Design; Binary Systems and Codes: Binary Numbers, Octal and Hexadecimal Numbers, Number Base Conversions, Arithmetic Operation with different Bases, Complements, Signed Binary Numbers, Binary Codes: BCD, Gray, ASCII and EBCDIC; Binary Logic and Logic Gates: AND, OR and NOT; Boolean Algebra and Logic Gates: Basic Definition, Basic Theorems, Boolean Functions; Standard Forms: Minterm and Maxterm, Simplification of Boolean Functions using SOP and POS; Logic Operations: NAND, NOR, Exclusive-OR and Equivalence, Integrated Circuits; Gate-Level Minimization: The Map Method, Two- and Three-Variable Map, Four-Variable Map, Product of Sums Simplification, Don’t-Care Conditions, NAND and NOR Implementation, The Tabulation Method, Simplification of Boolean Functions using Tabulation Method; Analysis and Synthesis of Combinational Circuits: Combinational Circuits, Analysis and Design Procedure, Binary Adders-Subtractor, Decoders and Multiplexers; Analysis and Synthesis of Sequential Circuits: Sequential Circuits, Latches, Flip-Flops: RS, D, JK and T, Analysis of Clocked Sequential Circuits, Design Procedure; Registers and Counters: Registers, Shift Registers, Synchronous Counters, Ripple Counters; Sequential Circuits with Programmable Logic Devices: Introduction, Random-Access Memory, Memory Decoding, Read-Only Memory, Programmable Logic Array.
Modes of Assessment:
Two 1-hour midterm exams (15% each); coursework (10%); Lab work (10%); Final (unseen) exam (50%)
Textbook and supporting material:
1- Mortis Mano, Digital Design, Prentice-Hall, 2002
2- Morris Mano, Charles R. Kime, Logic and computer design fundamentals, Pearson Prentice Hall, 2004
4- Kandel Langholz, Digital Logic Design, Prentice Hall, 1988.
5- Rafiquzzaman & Chandra, Modern Computer Architecture, West Pub. Comp., 1988.
750232, Computer Architecture Providing Department: Computer Science, Faculty of IT
Credit: 3 credit hours
The module will emphasize on the following knowledge areas: assembly level machine organization, memory system organization and architecture, interfacing and communication, functional organization, and alternative architectures.
Teaching Method: 32 hours Lectures (2 per week) + 12 hours Tutorials (0-1 per week) + 4 hours Seminars/Presentations
A student completing this module should:
Know what actions are taken at the machine level during the user's efforts for running a code written in high level language. (A)
Know what micro-actions are taken within a CPU during the machine's efforts for running a machine level code. (A)
Know the basic structure of a typical RISC and CISC processor. (A)
Understand how memory hierarchy and pipelining affect the performance of a processor. (A)
Understand the communication (input/output) issues.
Know the common blocks required in a typical computer system.
Be a knowledgeable consumer when it comes to the selection of appropriate computer hardware. (B)
Be able to prepare and deliver a written report. (C)
Assessment of Learning Outcomes:
Learning outcomes (1-7) are assessed by examinations, tutorials. Learning outcome (8) is assessed by assignments and seminars.
Contribution to Programme Learning Outcomes
A2, A3, A4, B2
Synopsis: Review of Basic Computer Architecture and Microprocessors; Von Neumann architecture: principles, instruction sets, instruction format, addressing modes, assembly/machine language programming, CISC versus RISC architectures, subroutine call and return mechanism; Control unit: hardwired, micro-programmed; Storage system and their technology: memory hierarchy, main memory organization and operations, cycle time, bandwidth and interleaving; cache memory: addressing mapping, block size, replacement and store policy; virtual memory: page table , TLB; I/O fundamentals: handshaking, buffering, programmed I/O, interrupts-driven I/O; Buses: types, bus protocols, arbitration, Direct Access Memory; Pipelining: principles, Instruction pipelines, Pipelines difficulties and solutions; Introduction to SIMD, MIMD.
Modes of Assessment:
Two midterm exams (15% each); Course work (10%); Seminars (5%); Tutorial Contribution (5%); Final Exam (50%)
Textbook and Supporting Material:
1- Patterson, D. A. and Hennessy, J. L. Computer Organization and Design: The Hardware/ Software Interface. 2nd Edition, (ISBN 1-558-604-91X), Morgan Kaufmann 1998
2- William Stallings, Computer Architecture & Organization: Design for Performance, Prentice Hall, 2000
750322, Design and Analysis of Algorithms Providing Department: Computer Science, Faculty of IT
Credit:3 credit hours
The aim of this module is to learn how to develop efficient algorithms for simple computational tasks and reasoning about the correctness of them. Through the complexity measures, different range of behaviours of algorithms and the notion of tractable and intractable problems will be understood. The module introduces formal techniques to support the design and analysis of algorithms, focusing on both the underlying mathematical theory and practical considerations of efficiency. Topics include asymptotic complexity bounds, techniques of analysis, and algorithmic strategies.
Teaching Methods: 38 hours Lectures (2 per week (including two 1-hour midterm exams)) + 10 hours Tutorials (average 1 hour per week)