Logistics

Logistics

• Logistics

• Midterm 1: Average 90/100. Well done!
• Midterm solutions online
• HW5 due date delayed until this Friday

• Last lecture

• Finished combinational logic
• Introduction to sequential logic and systems

• Today

• Memory storage elements
• Latches
• Flip-flops
• State Diagrams

Door combination lock

• Door combination lock

• Enter three numbers in sequence and the door opens
• As each number is entered, press ‘new’
• If there is an error the lock must be reset
• After the door opens the lock must be reset
• Inputs: Sequence of numbers, reset, new
• Outputs: Door open/close
• Memory: Must remember the combination
• Memory: Must remember which state we are in

Memory storage elements

• Memory storage elements

• In order to do fun problems like the door combination lock, we must know the building blocks (like how you had to learn AND and OR before you could do functional things). Be patient --- once you know these elements, you can build a lot of meaningful functions

• State diagrams

• For combinational logic, truth table was an invaluable visualization tool for a function. For sequential logic, state diagram serves as a way to visualize a function.

Two inverters can hold a bit

• Two inverters can hold a bit

• As long as power is applied

• Storing a new memory

• Temporarily break the feedback path

Cross-coupled NOR gates

• Cross-coupled NOR gates

• Can set (S=1, R=0) or reset (R=1, S=0) the output

Truth table and timing

• Truth table and timing

Static 0 hazards can set/reset latch

• Static 0 hazards can set/reset latch

• Glitch on S input sets latch
• Glitch on R input resets latch

How do we characterize logic circuits?

• How do we characterize logic circuits?

• Combinational circuits: Truth tables
• Sequential circuits: State diagrams

• First draw the states

• States  Unique circuit configurations

• Second draw the transitions between states

• Transitions  Changes in state caused by inputs

Begin by drawing the states

• Begin by drawing the states

• States  Unique circuit configurations
• Possible values for feedback (Q, Q')

The 1–1 state is transitory

• The 1–1 state is transitory

• Either R or S “gets ahead”
• Latch settles to 0–1 or 1–0 state ambiguously
• Race condition  non-deterministic transition
• Disallow (R,S) = (1,1)

Output depends on clock

• Output depends on clock

• Clock high: Input passes to output
• Clock low: Latch holds its output

• Latches are level sensitive and “transparent”

Input sampled at clock edge

• Input sampled at clock edge

• Rising edge: Input passes to output
• Otherwise: Flip-flop holds its output

• Flip-flops can be rising-edge triggered or falling-edge triggered

Edge triggering is difficult

• Edge triggering is difficult

• You can do this at home:
• Label the internal nodes
• Draw a timing diagram
• Start with Clk=1

Full name: Toggle flip-flop

• Full name: Toggle flip-flop

• Output toggles when input is asserted

• If T=1, then Q  Q' when CLK 
• If T=0, then Q  Q when CLK 

Clear and Preset set flip-flop to a known state

• Clear and Preset set flip-flop to a known state

• Used at startup, reset

• Clear or Reset to a logic 0

• Synchronous: Q=0 when next clock edge arrives
• Asynchronous: Q=0 when reset is asserted
• Doesn't wait for clock
• Quick but dangerous

• Preset or Set the state to logic 1

• Synchronous: Q=1 when next clock edge arrives
• Asynchronous: Q=1 when reset is asserted
• Doesn't wait for clock
• Quick but dangerous