Power distribution R&D for atlas slhc upgrades Maurice Garcia-Sciveres



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Power distribution R&D for ATLAS sLHC upgrades

  • Maurice Garcia-Sciveres

  • Lawrence Berkeley National Lab

  • SiD tracking meeting


Power lines

  • Problem of “long” distance electrical power distribution is not new

  • The novelty is that “long” is getting shorter

  • The relevant distance scale turns out to be the load operating voltage

  • Wrong units? Voltage is driven by oxide thickness inside the IC: units of length.

  • => Miniaturization inside IC also affects distances outside IC!

  • Eventually all power distribution distances become “long” => can only be solved at IC level



ATLAS pixel detector cable plant

  • Built in the traditional way



Scaling from present pixel detector with same cable plant down to PP2



Options well known,

  • Once accepted that we are dealing with long distance power transmission

    • Most ideas discussed today can be found in patents filed by Tesla well before 1900.


Existing efforts

  • There is a combined ATLAS R&D proposal:

  • Serial power:

    • SP demonstrator pixel modules have been produced at Bonn some time ago
    • Plan to make realistic serial power stave prototype in the near term
    • SCT implementing serial power with external regulators
    • More recent but also more prototyping work in SCT at present (RAL, LBNL)
  • DC-DC

    • Switched capacitor development at LBL
      • 2 version of ASIC submitted 1 month ago
      • This should produce a real regulator ready to power SCT stave prototypes and pixel modules but late summer.
    • Magnetic “buck” converter
      • Work started by Satish Dawn of Yale >1 year ago. Evaluate commercial parts and options for industry partnership
      • Parallel effort started at CERN in 2006. Significant manpower. Plan is to design a magnetic regulator controller and build a regulator from the ground up
      • Need to evaluate AC magnetic field issues.


Why switched capacitors?

  • Commercial DC-DC down-converters for power applications are all inductive.

  • Why then study switched capacitors for power?

    • Cannot use ferrites in magnetic field => performance penalty for magnetic converters
    • Fringe AC magnetic fields may produce pickup in detectors (must study case-by-case)
    • Ceramic capacitor miniaturization makes great advances year after year (air-core inductors cannot be improved).
    • Over-voltage safety considerations


Switched capacitor credits

  • IC design: Peter Denes

  • Simulation: Bob Ely, Peter Denes

  • Testing (so far only first prototype): Bob Ely, Seung Ji, Sami Hynynen, M. Garcia-Sciveres



Test configuration used: divide-by-4 stack

  • Phase 1 - Charge



Other configurations

  • Many capacitor arrangements are possible with different advantages

    • Minimum number of capacitors for a given ratio (less than for stack)
    • Minimum voltage drop across switches (more than for stack), etc.
  • Problem has been solved in general: Makowski, D. Maksimovic, "Performance limits of switched capacitor DC-DC converters," IEEE PESC, 1995 Record, pp. 12151221)



First prototype test chip

  • 50V (s-d) 0.35m HV CMOS process

  • Minimum size (adequate for ~100mA)

  • Switch transistors only- no auxiliary circuitry

  • Learned about process simulation, radiation hardness, and bulk isolation

  • Did not work as a useful converter due to bulk isolation problems

  • Results presented at 12th Workshop on Electronics for LHC and Future Experiments, http://ific.uv.es/lecc06/



HV Transistor characteristics after irradiation

  • The most important result is that the drain source resistance has increased by about 10%

  • Measured Rds also exceeded model predictions even before irradiation.

  • => Increased switch size.



Second prototype

  • Same 50V 0.35m HV CMOS process

  • Submitted February 2007 (expected back in May)

  • Sized for 1A output. 4.3 x 4.9 mm

  • Contains auxiliary circuits.

  • All capacitors external

  • All clocks external



Top level schematic



Simulation results 1



Simulation results 2



Simulation results 3



Serial power vs. DC-DC trade-offs

  • Power: Both increase power at/near the module by a similar amount

  • Mass: Serial power is in principle less massive because regulators can be built into chips.

  • Radiation: SP naturally rad-hard if regulators built into chips. DC-DC not yet rad-hard enough

  • Generality: DC-DC can be an off-the-shelf solution. A given converter can be used in several applications

  • Complexity: With SP the detector basic unit is a super-module. With DC-DC the basic unit is still a module.

  • Control: individual module control is simple with DC-DC, not with SP. With DC-DC module voltages are adjustable- not easily with SP.

  • Cable reduction: Both reduce copper mass by same amount. SP also reduces the cable count bu default. DC-DC allows trade-off between cable count and control granularity.



Serial power implementation

  • Regulators can be external or inside readout chips

  • Production pixel readout chips already have internal regulators built-in (but not used).

    • This shows that the serial power pixel R&D has a long history by now


Why is there no conductive interference (noise) between serial powered modules?



Serial-powered strip sensors



Serial power references



Conclusion

  • Powering has become a hot topic with lots of work going on

  • Expect usable prototype DC-DC converters by year’s end

  • Focus tends to be on powering existing chips, because that’s what people can make tests on

  • Reduction of current at the source (chip) has NOT YET received nearly as much attention within HEP. It should

  • How do we reduce the analog current keeping good performance?

  • How do we reduce the digital current?

    • An extreme is stacked logic domains- serial power inside the chip. Reference: http://www.bioee.ee.columbia.edu/
    • Less aggressive approaches are possible. I/O protocol. Clock distribution. Architecture.




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