Sri venkateswara college ofengineerin computer science and engineering

SRI VENKATESWARA COLLEGE OFENGINEERIN

COMPUTER SCIENCE AND ENGINEERING

CS6303-COMPUTER ARCHITECTURE

QUESTION BANK FOR CAT II

PART A (2 MARKS)

1. 
   Define datapath.
   
2. 
   What are the first two steps identical for every instruction?
   
3. 
   What are the datapath elements?
   
4. 
   What is program counter?
   
5. 
   What is instruction memory?
   
6. 
   What is the difference between adder and ALU?
   
7. 
   Draw the datapath for fetching the instruction.
   
8. 
   What is register file?
   
9. 
   What are the two elements needed to implement R-format ALU operation?
   
10. 
    What is the function of sign extension unit?
    
11. 
    What are units needed to implement load and store instructions?
    
12. 
    How will you calculate branch target address?
    
13. 
    What is branch taken and branch not taken?
    
14. 
    Draw the datapath for branch.
    
15. 
    Write R-type, I-type and J-type instruction format.
    
16. 
    What are the 9 control signals in the datapath?State their functions.
    
17. 
    Write down the steps to execute R-type instruction.
    
18. 
    Write down the steps to execute load instruction.
    
19. 
    Write down the steps to execute branch instruction.
    
20. 
    How does destination address for a jump instruction formed?
    
21. 
    What is pipelining?
    
22. 
    What are the MIPS pipeline stages?
    
23. 
    What are pipeline registers?
    
24. 
    What is the difference between single cycle and pipelined implementation?
    
25. 
    Draw the pipeline diagram for the following instructions
    

Lw $to,20($t1)

Sub $s1,$s2,$s3

26. 
    How 9 control lines are shuffled into 3 groups corresponding to last 3 pipeline stages?
    
27. 
    What is pipeline hazard?
    
28. 
    What are the different types of hazards?
    
29. 
    What is structural hazard?
    
30. 
    What is data hazard?
    
31. 
    What is control hazard?
    
32. 
    What is the technique used for handling data hazard?
    
33. 
    What is pipeline stall or bubble?
    
34. 
    What is the function of hazard detection unit?
    
35. 
    What is nop?
    
36. 
    What is dynamic branch prediction?
    
37. 
    What is branch delay slot and delayed branching?
    
38. 
    What are the three ways in which delay slot can be scheduled?
    
39. 
    What is exception and interrupt?
    
40. 
    What is Interrupt handler code?
    
41. 
    Give example for exception.
    
42. 
    What is EPC and cause register?
    
43. 
    What is ILP?
    
44. 
    What are the two primary methods for increasing the potential amount of ILP?
    
45. 
    What are the two ways to implement a multiple issue processor?
    
46. 
    What is static multiple issue?
    
47. 
    What is dynamic multiple issue?
    
48. 
    What is the difference between static multiple issue and dynamic multiple issue processor?
    
49. 
    How instructions are issued in a simple two issue MIPS processor?
    
50. 
    What are the additional hardware needed to issue an ALU and a data transfer instruction in parallel?
    
51. 
    What is use of reordering the instructions?
    
52. 
    What is data dependency?
    
53. 
    What is name or anti dependency?
    
54. 
    What is loop unrolling?
    
55. 
    What are the limitations of loop unrolling?
    
56. 
    What is register renaming?
    
57. 
    What are the three major units of dynamic pipeline scheduling?
    
58. 
    What are reservation stations?
    
59. 
    What is reorder buffer?
    
60. 
    What is out of order execution?
    
61. 
    What is dynamic scheduling?
    
62. 
    What is speculation?
    
63. 
    What is Flynn’s classification?
    
64. 
    What is instruction stream and data stream?
    
65. 
    What are SISD, SIMD, MISD, and MIMD?
    
66. 
    Give example for SISD and SIMD architecture.
    
67. 
    What is thread?
    
68. 
    What is thread level parallelism?
    
69. 
    What is data level parallelism?
    
70. 
    What is multithreading?
    
71. 
    What are the three approaches of hardware multithreading?
    
72. 
    Explain Fine grained multithreading.
    
73. 
    Explain coarse grainedmultithreading?
    
74. 
    What is SMT?
    
75. 
    What are the advantages and dis advantages of Fine grained and coarse grained multithreading?
    
76. 
    What are the limitations of SMT?
    
77. 
    Define multicore processor.
    
78. 
    What is SMP?
    
79. 
    What are UMA and NUMA?
    
80. 
    What is synchronization?
    
81. 
    What is lock?
    

PART B

1. 
   Explain datapath for the memory instruction and R-type instruction with neat diagram.
   
2. 
   Draw and explain the datapath for the core MIPS architecture.
   
3. 
   Draw and explain the datapath with the control unit.
   
4. 
   Draw and explain simple control and datapath to handle jump instruction.
   
5. 
   Differentiate single cycle vs pipelined execution with example.
   
6. 
   With neat diagram explain pipelined version of thedatapath.
   
7. 
   Explain the 5 pipe stages of lw instruction with diagram.
   
8. 
   Explain the pipe stages of sw instruction with diagram.
   
9. 
   Draw the pipe diagram for any 5 instructions.
   
10. 
    Explain in detail about pipelined control.
    
11. 
    Write short notes on structural hazard.
    
12. 
    Explain various techniques for handling data hazard.
    
13. 
    Explain in detail various schemes for resolving control hazard.
    
14. 
    Explain forwarding/bypassing technique.
    
15. 
    Explain in detail dynamic branch prediction schemes.
    
16. 
    Explain with example the various ways in which branch delay slot can be scheduled?
    
17. 
    Write notes on exception and interrupt handling in MIPS.
    
18. 
    Explain various compiler techniques for increasing ILP.
    
19. 
    Explain in detail the two ways to implement multiple issue processors.
    
20. 
    Explain static multiple issue code scheduling for effectively exploiting parallelism in a multiple issue processor.
    
21. 
    Explain with example loop unrolling for multiple issue pipelines.
    
22. 
    Explain with neat diagram dynamic pipeline scheduling.
    
23. 
    Write note on parallel processing challenges.
    
24. 
    Explain Flynn’s classification with neat diagram.
    
25. 
    Explain various hardware multithreading techniques
    
26. 
    Describe the terms fine grained, coarse grained and simultaneous multithreading.
    
27. 
    What are multi core processors? Explain how multicore processors works?
    
28. 
    Explain SMP architecture with neat diagram.