The internal structure of the ics



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The internal structure of the ICs

  • The internal structure of the ICs

  • ROM Types and RAM



How a ROM works

  • How a ROM works



The basic structure

  • The basic structure



Arranged in blocks

  • Arranged in blocks



Table 9-5

  • Table 9-5

    • Type Tech ReadCyc WrCyc Comments
    • MASK ROM NMOS 10-100ns 4 weeks Write once, low pwr
    • CMOS
    • MASK ROM Bipolar <100ns 4 weeks Write once, h pwr
    • low density
    • PROM Bipolar <100ns 10-50us/byte Write once, h pwr
    • EPROM NMOS 25-200ns 10-50us/byte Reusable, low pwr
    • CMOS
    • EEPROM NMOS 50-200ns 10-50us/byte 10,000 to 100,000
    • writes per location


Erasable Programable Read Only Memory

  • Erasable Programable Read Only Memory



Uses a floating gate for the FET at each bit location

  • Uses a floating gate for the FET at each bit location

  • User uses a programming voltage that causes a temporary breakdown in the dielectric between the gate and the floating gate to charge it.

  • When programming voltage is removed the charge stays

  • How long? EPROM manufacturers “guarantee” properly programmed bit has 70% of charge after 10 years.

  • Use UV light to erase



Electrically Erasable PROM

  • Electrically Erasable PROM

  • Like the EPROM only electrically erasable in circuit.

  • Many times referred to a “flash” programmable memory

  • Very slow on writes so not a substitute for RAM



xROM

  • xROM



General timing parameters

  • General timing parameters



Access time from address – tAA

  • Access time from address – tAA

  • Access time from chip select - tACS

  • Output-enable time - tOE

  • Output-disable time - tOZ

  • Output-hold time - tOH



Memory to store and retrieve data when more than F/Fs

  • Memory to store and retrieve data when more than F/Fs

  • A few types

  • Static RAM – SRAM

    • As long as power is maintained data is held


The data storage

  • The data storage



Internal – an arrangement of storage sturctures

  • Internal – an arrangement of storage sturctures



Timing for write similar (see Fig 9-23)

  • Timing for write similar (see Fig 9-23)



Next step in memory is Synchronous SRAM which has a clocked interface for control, address and data.

  • Next step in memory is Synchronous SRAM which has a clocked interface for control, address and data.

  • Then comes DRAM – dynamic ram

  • In DRAM data is stored

  • in a semiconductor

  • capicator.



A read sees the bit line precharged to high.

  • A read sees the bit line precharged to high.

  • The word line is then activated

  • If cell stores a 0 then there is a small drop on the voltage on the bit line

  • This is monitored by a sense amp which provides the value stored

  • Value must be written back after the read.



Charge stored leaks off over time

  • Charge stored leaks off over time

  • Must restore the values stored

    • A 4096 row DRAM – refresh every 64ms
    • Thus each row every 15.6 usec
  • Larger DRAMs are banks of smaller



Double data rate SDRAM

  • Double data rate SDRAM

  • Double the data transfer rate of an SDRAM by transferring on both edges of the clock

  • Access and setup times are the same as SRAM

  • Increased data thruput as data is transferred in blocks.





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