The objectives of this laboratory are: To design various latch and flip-flop circuits



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#4147

Latches and Flip-Flops


Objectives


The objectives of this laboratory are:

  • To design various latch and flip-flop circuits

  • To test various latch and design circuits

  • To measure the non-ideal properties of your circuits and compare the performance of your flip-flop(s) with that of a pre-packaged flip-flop

Latches and flip-flops are the primitive storage devices in sequential circuits. In this laboratory, you will study their functional and temporal behavior and develop some insights about sequential circuit operation in general.



Latches


A latch is an asynchronous digital circuit that has two stable states0 and 1that can be used to store state information.
SR Latch


Figure 4.1 A NOR-based SR Latch


One of the most fundamental latches is the SR latch, where S and R stand for Set and Reset. Figure 4.1 shows the logic diagram of an SR latch built using cross-coupled NOR gates. The stored bit is available at the output marked Q; its complement is available at output . While the S and R inputs are both low, feedback maintains the two outputs in a constant state.http://upload.wikimedia.org/wikipedia/commons/thumb/5/53/rs_flip-flop_%28nor%29.svg/200px-rs_flip-flop_%28nor%29.svg.png

When R = 1 and S = 0, output Q will go to 0 regardless of its value before R was set to 1, and that forces to 1 after a brief delay. Thus, R resets the output to 0. When R = 0 and S = 1, becomes 0 and Q becomes 1. Thus, input S sets the latch.

When R = S = 1, both Q and become 0, and are no longer complementary to each other. At this point, if both R and S are simultaneously switched to 0, both outputs will be forced to become 1, which in turn will try to force both outputs to become 0, and so on. If both NOR gates and the associated wires have the same delays, both outputs will oscillate indefinitely with a period of 2 gate delays. In reality, the two path delays will not be identical, forcing the latch to go to a stable state. Because the final output state will vary from one latch to another, the input combination R = S = 1 is not usually applied. It is up to the circuit designer to insure that this condition never appears.http://upload.wikimedia.org/wikipedia/commons/thumb/9/92/sr_flip-flop_diagram.svg/200px-sr_flip-flop_diagram.svg.png


Figure 4.2 A NAND-based Latch
An alternate model of the SR latch can be built with NAND gates, as shown in Figure 4.2. Set and reset now become active low signals, denoted S and R respectively. Otherwise, operation is identical to that of the SR latch. Historically, the NAND-basedlatch has been predominant, despite the notational inconvenience of active low inputs.







Gated SR Latch

For many applications it is helpful for the latch to have a "lockdown" period during which the outputs cannot change regardless of what is happening at the inputs. During this period the output is truly "latched" to its memory value. Gated latches use a clock input (also referred to as a gate or enable input) to implement such a lockdown period. The latch inputs are ignored except when the clock signal is asserted. This effectively makes time discrete, since we do not care what happens when the clock is not asserted.


Figure 4.3 A NAND-based Gated SR Latch
Figure 4.3 shows a gated SR latch implemented using NAND gates. When C = 1, the latch is said to be enabled, i.e., the outputs can respond to the inputs, and the circuit behaves like an ungated latch. For instance, when S = 1 and R = 0, then the upper input to the top right NAND gate is = 0, and that to the lower right gate is = 1, resulting in Q = 1 and = 0.

By contrast, when C = 0, the gate is shut, i.e., the latch is disabled, the left pair of NAND gates keep both latch inputs at 1, maintaining Q and at constant values.



Gated D Latch


Figure 4.4 A NAND-based Gated DLatch


The gated D latch, shown in Figure 4.4, avoids the “forbidden” inputs SR = 11 using an inverter that connects the S and R inputs. Other than the gate input C, there is only one other input, D. When C = 1, this is like a gated latch that has been enabled, except that the inputs to the first set of NAND gates cannot be 00 or 11. Thus a gated D-latch may be considered as a single-input synchronous SR latch. This configuration prevents the restricted 11 input combination from appearing. It is also known as transparent latch or data latch. The word transparent comes from the fact that, when the clock input is on, the D input value propagates directly through the circuit to output Q.

The gated D latch can be implemented in different ways. Figure 4.5 shows another way of building the gated D latch.


Figure 4.5 An Alternate NAND-based Gated D Latch

Flip-Flops


With each of the circuit designs (latches) discussed so far, the outputs can change at any time, as can the inputs. That leads to problems if the inputs switch, and then before the outputs settle into their new state, the input switches again. Or if the outputs are near the "metastable" state half-way between 0 and 1 and the inputs switch to the hold values. Timing requirements such as minimum pulse width, setup and hold times, and allowance for propagation delays are impossible to guarantee with asynchronous digital logic circuits such as latches.

One way to guard against such problems is to make sure that there is ample time for all propagation delays, that input signals cannot change too fast, and that there is no chance for one of the questionable inputs to arise.

The simplest, and most common, way to do this is to make the clock input a periodic signal, and to synchronize the input signals with the clock, resulting in synchronous circuits called flip-flops.

4.3.1 Master-Slave D Flip-Flop

Flip-flops respond to input signals only when the clock transitions from 1 to 0 or 0 to 1. One way to implement this edge-triggering behavior is to use two D latches in series as shown in Figure 4.6. The clock inputs of the two latches are complementary to each other. When the clock signal is low, the second latch is opaque, and so the output Q remains constant. At the same time, the first latch is transparent and so any changes in D are transmitted to its output. At the time the clock signal transitions from low to high, the output of the first latch becomes locked and is transmitted to the output of the second latch. It is called master–slave because the second latch in the series only responds to changes in the output of the first (master) latch.



http://upload.wikimedia.org/wikipedia/commons/thumb/3/37/d-type_flip-flop_diagram.svg/600px-d-type_flip-flop_diagram.svg.png


Figure 4.6 A Positive Edge Triggered Master-Slave D Flip-Flop



Edge-Triggered D Flip-Flop

The master-slave flip-flop is an adequate design for a D flip-flop. There are other types of flip-flops, not discussed here, for which it does not work well. The master-slave J-K flop-flop, for example, exhibits a phenomenon known as ones-catching. A spurious 1 on the input will be latched and propagated to the output even if the input returns to 0 before the end of the clock period.

The problems of hazards and ones-catching can be solved by designing a storage circuit that both samples its inputs and stores data based on the transition of a clock pulse. If the combinational parts of a circuit could settle during the time the clock signal was true, and the storage part of the circuit sampled the input and saved the result when the clock changed from true to false, there will be no problems with hazards at the output nor with ones catching. A storage circuit like that is called an edge-triggered flip-flop.

Figure 4.7 shows a positive edge-triggered D flip-flop that does not use the master-slave approach. It uses 3 SR latches. The bottom latch stores the D value and the top latch stores . The latch at the output prevents the output from changing except during a 0-to-1 transition of the clock.



Figure 4.7 A Positive Edge Triggered D Flip-Flop

Pre-lab Preparation
You will be told to do one of the following labs: 4A – 4L. Look at the table below for the latches and flip-flops that correspond to your lab.


Lab

SR Latch Type

Flip Flop Type

4A

NOR

Positive Edge Triggered D

4B

NOR

Negative Edge Triggered D

4C

NOR

Positive Edge Triggered T

4D

NOR

Negative Edge Triggered T

4E

NOR

Positive Edge Triggered JK

4F

NOR

Negative Edge Triggered JK

4G

NAND

Positive Edge Triggered D

4H

NAND

Negative Edge Triggered D

4I

NAND

Positive Edge Triggered T

4J

NAND

Negative Edge Triggered T

4K

NAND

Positive Edge Triggered JK

4L

NAND

Negative Edge Triggered JK


Part I – SR Latch

  1. Design a gated SR latch using NOR/NAND gates.

  2. Draw the logic diagram and wiring diagram for the latch using the available CMOS chips.

  3. Use PSpice to simulate the SR latch and plot the output and the input signals as a function of time when you use a synchronous mod-4 counter to generate the input signals.


Part II – Master-Slave SR Flip-Flop

  1. Design a master-slave SR flip-flop using the SR latch designed above in Part I.

  2. Draw both the logic diagram and wiring diagram for the slip-flop using the available CMOS chips.

  3. Use PSpice to simulate the flip-flop. Use a synchronous mod-8 counter to generate all possible combinations for the Set and Reset signals, including the SR = 11 combination. Use the two most significant bits of the counter output for the Set and Reset signals. Use the same clock to drive the counter and your flip-flop, but invert the clock before connecting it to the flip-flop.


Part III – Edge-Triggered Flip-Flop

  1. Design the designated flip-flop using the “truly” edge-triggered approach.

  2. Draw both the logic and wiring diagrams.

  3. Use PSpice to simulate the flip-flop. Use a 100 kHz “digclock” with a duty factor of 50% for the clock signal and a 50 kHz “digclock” with a 70% duty factor as the input to the flip-flop (for the JK flip-flop, tie the J and K together). Plot both clocks and the output of the flip-flop versus time.


Pre-lab Questions

Attach the results of your pre-lab work (drawings, simulations, etc.) to this question sheet.



  1. Explain the difference between a latch and a flip-flop.

  2. Why is the condition S = R = 1 not allowed for an SR latch?

  3. There is no such thing as an ungated D latch. Why?

  4. What are the differences between the D, T, and JK flip-flops?

  5. Did you observe any glitches in the simulation results? If so, where?

  6. What are setup and hold times for a flip-flop? Why are they important?

  7. What is a master-slave flip-flop?


In-lab Procedure

  • Bring flash drives to store your traces.

  • Ask the TA questions regarding any procedures about which you are uncertain.

  • Turn off all power supplies any time that you make any change to the circuit.

  • Do NOT apply more than 5 V to the circuit at any time.

  • Arrange your circuit components neatly and in a logical order.

  • Compare your breadboard carefully with your circuit diagram before applying power to the circuit.

  • Complete the following tasks:

Part I – SR Latch


  1. Construct the SR latch.

  2. Manually test all possible (4) input combinations with clock C = 1 and record both the input and output voltages with a DMM.

  3. Set the clock high, tie S and R together to the output of the function generator “sync out” and set the frequency to 100 kHz. Observe the output on a DLA and note any irregularities.

Part II – Master-Slave SR Flip-Flop


  1. Construct the master-slave SR flip-flop.

  2. Set the function generator to 100 kHz and use it to drive both your SR flip-flop and a synchronous mod-8 counter. Use the two most significant bits for the S and R inputs of your flip-flop. Plot the clock, Set, Reset, and the two SR flip-flop outputs on the DLA.

  3. Measure the time delay between the clock and the output signal, as well as the delays between the clock and the intermediate switching circuit signals.

Part III – Edge-Triggered Flip-Flop


  1. Construct the edge-triggered flip-flop.

  2. If using a JK or T flip-flop, tie the inputs to 5 V. Otherwise, tie the input to . Drive the flip-flop clock with a 100 kHz square wave.

  3. Plot the clock, the input, Q, and simultaneously on the oscilloscope.

  4. Measure the delay time of the output on the oscilloscope. Record the output voltage for both the 0 and 1 states.

  5. Increase the clock frequency and note if and when the circuit fails.

Part IV – Pre-packaged D Flip-Flop


  1. Use one of the D flip-flops in chip 4013, and tie the D input to . Drive the clock input with a 100 kHz square wave.

  2. Plot the clock, the D input, Q, and simultaneously on the oscilloscope.

  3. Measure the delay time of the output on the oscilloscope. Record the output voltage for both the 0 and 1 states.

  4. Increase the clock frequency and note if and when the device fails.



Helpful Hints


  1. You do not need to design the circuits of this lab from scratch; you should be able to find the designs in a digital logic textbook.

  2. You can make inverters by tying together all of the inputs of a NOR or NAND gate. This may be a useful way to reduce the chip count.

  3. Try to arrange your components on the breadboard in a similar arrangement as on your wiring diagram.


Post-lab Analysis

Generate a lab report “following” the outline given in blackboard. Mention any difficulties encountered during the lab. Describe any results that were unexpected and try to account for the origin of these results (i.e. explain what happened). In addition, answer the following questions:


Part I – SR Latch


  1. What are the minimum required pulse widths for setting and resetting your SR latch?

  2. Comment on the differences in the simulation and experimental results for the SR latch.

Part II – Master-Slave SR Flip-Flop


  1. What is the set up time of the flip-flop that you implemented?

  2. What is the minimum required clock pulse width to insure that your D flip-flop is set?

  3. How did the measured delay time compare to the simulated delay time?

  4. Did you expect to see any glitches in the output measurements? Why, or why not?

  5. Did you observe any glitches in the output measurements? If so, explain their origin.

Part III – Edge-Triggered Flip-Flop


  1. How did the delay time of the edge-triggered flip-flop compare with those of the master-slace flip-flop?

  2. How did the voltage levels of these two flip-flops compare?


Part IV – Pre-packaged D Flip-Flop

  1. If the pre-packaged D flip-flop failed at some frequency during experimental step 15, what was the failure mechanism?


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