X All-optical flip-flops based on semiconductor technologies
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- 4. SOA-based clocked flip-flops
- 4.1 Clocked SR flip-flop
- 4.2 Clocked D flip-flop
Semiconductor Technologies 356
of about 100ns. Experimental measurements (Fig. 12 (a)) show that the building-up process of one state takes place step by step and each step corresponds to a cavity round-trip time equal to 100ns. The total rising edge behavior lasts several hundreds of ns. The experimental falling edge behavior is shown in Fig. 12 (b), with a transition time of 5ns, equal to the input pulse edge. Dynamics behavior of the two SOA-based coupled lasing cavities has been analyzed through simulations as well, whose details can be found in (Barman et al., 2007). Assuming the same parameters of the experimental setup (cavity length and cavity loss, injected pulses edge time and average power), as can be observed in Fig. 12 (c)-(d), simulation results for rising and falling edges are in good agreement with experimental measurements, confirming the step behavior of the rising edge and at the same time a falling edge as fast as the input pulse edge. We also simulated an integrated version of this flip-flop, considering 2mm cavity length and 0.5mm SOA length. Results predict 12ps falling time and ~40ps rising time with injected input pulsewidth of 12ps and pulse energy of 15.6fJ, comparable with the results of one of the latest optical flip-flop integrated version (Hill et al., 2004).
Most of the all-optical flip-flops proposed in literature are non-clocked devices, whose output changes immediately following the set/reset signals, thus they are also referred to as Set-Reset (SR) latch. As a digital device that temporarily memorizes the past input signal and processes it with current inputs, optical flip-flop is expected to be synchronized with a system clock, and to work in a timely programmed mode. Moreover, in some complicated optical computing applications such as optical shift registers or counters, various types of clocked flip-flops are necessary, such as SR, D, T, and JK flip-flops. Starting from the basic structure defined in the previous paragraph, here we show clocked all-optical flip-flops including SR, D, T, and JK types, exploiting also AND logic gates based on nonlinear effects in SOA (Wang et al., 2009, a).
4.1 Clocked SR flip-flop The characteristic table of the set/reset (SR) flip-flop is shown in Fig. 13 (a). If S=R=0, the flip-flop remains at its previous state; if S=1 R=0, it is set to “state 1”; if S=0 R=1, it is set to “state 0”. S=R=1 is forbidden since the flip-flop is unstable in this case. The setup of clocked SR flip-flop is shown in Fig. 13 (b): it consists of two AND gates and one SR latch. “AND 1” and “AND 2” perform AND function between the clock pulse and S and R, respectively. The outputs of “AND 1” and “AND 2” are connected to the “Set” and “Reset” ports of the latch respectively. The operation principle of this clocked flip-flop is shown in Fig. 13 (c): when a clock pulse comes, if S=R=0 it can not pass through either “AND 1” or “AND 2”, so “Set” and “Reset” ports receive no pulse and the latch maintains its previous state (Q next =Q); if S=1 R=0, the clock pulse can pass through “AND 1” but is blocked by “AND 2”, so only “Set” receives a pulse and the latch is set to “state 1” (Q
next =1); if S=0 R=1, the clock pulse can pass through “AND 2” but is blocked by “AND 1”, so the latch is set to “state 0” (Q next
=0). S=R=1 is forbidden since the latch is unstable when “Set” and “Reset” receive pulses simultaneously. The flip-flop is clocked because it only changes state when a clock pulse comes, according to the S and R values at that time. S and R values at any other time are ignored.
Forbidden N/A 1 1 Reset 0 1 0 Set
1 0 1 Hold state Q 0 0 Comment
Q next
R S Forbidden N/A 1 1 Reset 0 1 0 Set
1 0 1 Hold state Q 0 0 Comment
Q next
R S
(a)
(b)
(c) Fig. 13. Clocked SR flip-flop: (a) characteristic table; (b) logic circuits; (c) working principle.
In Fig. 14 the experimental operation of the clocked SR flip-flop is reported. The clock pulse has a repetition rate of 200kHz with a pulse-width of 1μs. S and R signals also have a pulse- width of 1μs but at a repetition rate of 50kHz, synchronized with the clock. The wavelengths of clock, S and R are λ CLK
=1554.1nm, λ S =1552.5nm and λ R =1550.5nm respectively, and the outputs of “AND 1” and “AND 2” are at λ 1 =2λ S -λ CLK =1550.9nm and λ 2 =2λ R -λ CLK =1546.9nm. The flip-flop only responses to the S and R values when a clock pulse comes, but ignores the S and R at any other time, in agreement with Fig. 13 (c).
The characteristic table of D flip-flop is shown in Fig. 15 (a). D represents the data signal. If D=0, the flip-flop is set to “state 0”; if D=1, the flip-flop is set to “state 1”. The setup of clocked D flip-flop is shown in Fig. 15 (b): “AND 1” gate performs AND function between the clock pulse and D, whereas “AND 2” performs AND function between clock and inverted D. The operation principle of D flip-flop is shown in Fig. 15 (c): when a clock pulse comes, if D=1 it can pass through “AND 1” but is blocked by “AND 2”, so only “Set” port receives a pulse and the latch is set to “state 1” (Q=1); similarly if D=0 the clock pulse can www.intechopen.com Yüklə 0,55 Mb. Dostları ilə paylaş:
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