Semiconductor Technologies
358
pass through “AND 2” but is blocked by “AND 1”, only “Reset” receives a pulse and the
latch is set to “state 0” (Q=0). The flip-flop is clocked because it only changes state when a
clock pulse comes, according to the D values at that time, but ignores D at any other time.
Set
1
1
Reset
0
0
Comment
Q
next
D
Set
1
1
Reset
0
0
Comment
Q
next
D
(a)
(b)
(c)
Fig. 15. Clocked D flip-flop: (a) characteristic table; (b) logic circuits; (c) working principle.
Fig. 16. Clocked D flip-flop operation.
In Fig. 16 clocked D type flip-flop operation is experimentally demonstrated. The clock
pulse has a repetition rate of 60kHz with a pulsewidth of 1μs; whereas D has a repetition
rate of 100kHz with a pulsewidth of 6μs. The wavelength of clock and D are λ
CLK
=1554.1nm
and λ
D
=1552.5nm respectively, so the output of “AND 1” is at λ
1
=2λ
D
-λ
CLK
=1550.9nm and
the output of “AND 2” is at λ
2
=λ
CLK
=1554.1nm, the same with the clock pulse. The flip-flop
only responses to the D values when clock pulses come, and therefore is clocked.
4.3 Clocked T flip-flop
The characteristic table of T flip-flop is shown in Fig. 17 (a). T represents the toggling signal.
If T=0, the flip-flop maintains its previous state; if T=1, the flip-flop changes its state. The
setup of clocked T flip-flop is shown in Fig. 17 (b). Different from SR and D flip-flops, in T
flip-flop, the next state is not determined by external control signals, such as S, R, and D, but
depends on the previous state, so feedback of output Q is used in T flip-flop to carry out the
toggling operation. “AND 1” performs AND function between the clock pulse and T;
whereas “AND 2” performs AND between the output of “AND 1” and the feedback output
Q. “AND 3” carries out AND function between output of “AND 1” and inverted Q. The
operation principle of T flip-flop is shown in Fig. 17 (c): when a clock pulse comes, if T=0 it
is blocked by “AND 1”, neither “Set” nor “Reset” receives pulse, and the latch remains at its
previous state. If T=1, the clock pulse can pass through “AND 1”; then, if Q=1 it can pass
through “AND 2” but is blocked by “AND 3”, so only “Reset” receives a pulse and the latch
toggles to “state 0” (Q=0); if Q=0 the clock pulse can pass through “AND 3” but is blocked
by “AND 2”, only “Set” receives a pulse and the latch toggles to “state 1” (Q=1). In this way,
the flip-flop is triggered by the clock pulse, changing its state if T=1, or maintaining its state
if T=0.
Toggle
Q
1
Hold state
Q
0
Comment
Q
next
T
Toggle
Q
1
Hold state
Q
0
Comment
Q
next
T
T
CLK
CLK
∩
T
Q
1
1
1
0
1
0
0
CLK
∩
T
∩Q
AND 3
Set
AND 2
Reset
0
AND 1
CLK
∩
T
∩Q
(a)
(b)
(c)
Fig. 17. Clocked T flip-flop: (a) characteristic Table; (b) logic circuits; (c) working principle.
Fig. 18. Clocked T flip-flop operation.
In Fig. 18 clocked T flip-flop operation is experimentally demonstrated. The clock pulse has
a repetition rate of 60kHz with a pulse-width of 1μs; whereas T has a repetition rate of
100kHz with a pulse-width of 6μs. The wavelength of clock pulse and T are λ
CLK
=1554.1nm
and λ
T
=1552.5nm respectively, so the output of “AND 1” is at λ
1
=2λ
T
-λ
CLK
=1550.9nm. The
flip-flop output, Q, has a wavelength of λ
Q
=1549.3nm, so the output of “AND 2” is at
λ
2
=2λ
Q
-λ
1
=1547.7nm and the output of “AND 3” is at λ
3
=λ
1
=1550.9nm, the same with the
output of “AND 1”. The flip-flop is clocked since the state toggling is only triggered when a
clock pulse comes and T=1.
4.4 Clocked JK flip-flop
The characteristic table of JK flip-flop is shown in Fig. 19(a), which could be considered as a
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All-optical lip-lops based on semiconductor technologies
359
pass through “AND 2” but is blocked by “AND 1”, only “Reset” receives a pulse and the
latch is set to “state 0” (Q=0). The flip-flop is clocked because it only changes state when a
clock pulse comes, according to the D values at that time, but ignores D at any other time.
Set
1
1
Reset
0
0
Comment
Q
next
D
Set
1
1
Reset
0
0
Comment
Q
next
D
(a)
(b)
(c)
Fig. 15. Clocked D flip-flop: (a) characteristic table; (b) logic circuits; (c) working principle.
Fig. 16. Clocked D flip-flop operation.
In Fig. 16 clocked D type flip-flop operation is experimentally demonstrated. The clock
pulse has a repetition rate of 60kHz with a pulsewidth of 1μs; whereas D has a repetition
rate of 100kHz with a pulsewidth of 6μs. The wavelength of clock and D are λ
CLK
=1554.1nm
and λ
D
=1552.5nm respectively, so the output of “AND 1” is at λ
1
=2λ
D
-λ
CLK
=1550.9nm and
the output of “AND 2” is at λ
2
=λ
CLK
=1554.1nm, the same with the clock pulse. The flip-flop
only responses to the D values when clock pulses come, and therefore is clocked.
4.3 Clocked T flip-flop
The characteristic table of T flip-flop is shown in Fig. 17 (a). T represents the toggling signal.
If T=0, the flip-flop maintains its previous state; if T=1, the flip-flop changes its state. The
setup of clocked T flip-flop is shown in Fig. 17 (b). Different from SR and D flip-flops, in T
flip-flop, the next state is not determined by external control signals, such as S, R, and D, but
depends on the previous state, so feedback of output Q is used in T flip-flop to carry out the
toggling operation. “AND 1” performs AND function between the clock pulse and T;
whereas “AND 2” performs AND between the output of “AND 1” and the feedback output
Q. “AND 3” carries out AND function between output of “AND 1” and inverted Q. The
operation principle of T flip-flop is shown in Fig. 17 (c): when a clock pulse comes, if T=0 it
is blocked by “AND 1”, neither “Set” nor “Reset” receives pulse, and the latch remains at its
previous state. If T=1, the clock pulse can pass through “AND 1”; then, if Q=1 it can pass
through “AND 2” but is blocked by “AND 3”, so only “Reset” receives a pulse and the latch
toggles to “state 0” (Q=0); if Q=0 the clock pulse can pass through “AND 3” but is blocked
by “AND 2”, only “Set” receives a pulse and the latch toggles to “state 1” (Q=1). In this way,
the flip-flop is triggered by the clock pulse, changing its state if T=1, or maintaining its state
if T=0.
Toggle
Q
1
Hold state
Q
0
Comment
Q
next
T
Toggle
Q
1
Hold state
Q
0
Comment
Q
next
T
T
CLK
CLK
∩
T
Q
1
1
1
0
1
0
0
CLK
∩
T
∩Q
AND 3
Set
AND 2
Reset
0
AND 1
CLK
∩
T
∩Q
(a)
(b)
(c)
Fig. 17. Clocked T flip-flop: (a) characteristic Table; (b) logic circuits; (c) working principle.
Fig. 18. Clocked T flip-flop operation.
In Fig. 18 clocked T flip-flop operation is experimentally demonstrated. The clock pulse has
a repetition rate of 60kHz with a pulse-width of 1μs; whereas T has a repetition rate of
100kHz with a pulse-width of 6μs. The wavelength of clock pulse and T are λ
CLK
=1554.1nm
and λ
T
=1552.5nm respectively, so the output of “AND 1” is at λ
1
=2λ
T
-λ
CLK
=1550.9nm. The
flip-flop output, Q, has a wavelength of λ
Q
=1549.3nm, so the output of “AND 2” is at
λ
2
=2λ
Q
-λ
1
=1547.7nm and the output of “AND 3” is at λ
3
=λ
1
=1550.9nm, the same with the
output of “AND 1”. The flip-flop is clocked since the state toggling is only triggered when a
clock pulse comes and T=1.
4.4 Clocked JK flip-flop
The characteristic table of JK flip-flop is shown in Fig. 19(a), which could be considered as a
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