After completing this module, you will be able to: After completing this module, you will be able to



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After completing this module, you will be able to:

  • After completing this module, you will be able to:

  • Describe the control sets of the slice flip-flops

  • Identify the implications of the control sets on packing



Control Sets

  • Control Sets

  • Designing Resets

  • Other Reset Considerations

  • Summary



All flip-flops are D type

  • All flip-flops are D type

  • All flip-flops have a single clock input (CLK)

    • Clock can be inverted at the slice boundary
  • All flip-flops have an active high chip enable (CE)

  • All flip-flops have an active high SR input

    • SR can be synchronous or asynchronous, as determined by the configuration bit stream
    • Sets the flip-flop value to a pre-determined state, as determined by the configuration bit stream
  • All flip-flops are initialized during configuration



All flip-flops in the 7 series FPGAs have a chip enable (CE) pin

  • All flip-flops in the 7 series FPGAs have a chip enable (CE) pin

    • Active high, synchronous to CLK
    • When asserted, the flip-flop clocks in the D input
    • When not asserted, the flip-flop holds the current value
  • Inferred naturally from RTL code



The flip-flop has a single active high SR port

  • The flip-flop has a single active high SR port

    • The SR port can be configured as either a synchronous set/reset or asynchronous preset/clear port
    • When asserted, the flip-flop output will be forced to the SRVAL attribute of the flip-flop
    • This attribute is extracted automatically from your RTL code based on your reset structure
  • The flip-flop also has an initialization value, INIT

    • This is the value loaded into the flip-flop during configuration, and when the global set reset (GSR) signal is asserted
    • This attribute can also be extracted from your RTL code by some synthesis tools


To infer asynchronous resets, the reset signal must be in the sensitivity list of the process

  • To infer asynchronous resets, the reset signal must be in the sensitivity list of the process

  • Output takes reset value immediately

    • Even if clock is not present
  • SRVAL attribute is determined by reset value in RTL code



Deassertion of reset should be synchronous to the clock

  • Deassertion of reset should be synchronous to the clock

  • Not synchronizing the deassertion of reset can create problems

    • Flip-flops can go metastable
    • Not all flip-flops are guaranteed to come out of reset on the same clock
  • Use a reset bridge to synchronize reset to each domain



A synchronous reset will not take effect until the first active clock edge after the assertion of the RST signal

  • A synchronous reset will not take effect until the first active clock edge after the assertion of the RST signal

  • The RST pin of the flip-flop is a regular timing path endpoint

    • The timing path ending at the RST pin will be covered by a PERIOD constraint on the clock


When the FPGA is configured, flip-flops are loaded with an initialization value

  • When the FPGA is configured, flip-flops are loaded with an initialization value

    • The value is determined by the INIT attribute
  • The INIT value can be restored by asserting the GSR net

  • The initial value of the reg/signal that is used for the flip-flop is extracted by the synthesis tool



All flip-flops and flip-flop/latches share the same CLK, SR, and CE signals

  • All flip-flops and flip-flop/latches share the same CLK, SR, and CE signals

    • This is referred to as the “control set” of the flip-flops
    • CE and SR are active high
    • CLK can be inverted at the slice boundary
  • If any one flip-flop uses a CE, all others must use the same CE

    • CE gates the clock at the slice boundary
    • Saves power
  • If any one flip-flop uses the SR, all others must use the same SR

    • The reset value used for each flip-flop is individually set by the SRVAL attribute


Eight registers per slice; all use the same control set

  • Eight registers per slice; all use the same control set

    • If the number of registers in a control set do not divide cleanly by eight, some registers will go unused
  • This is of concern for designs that have lots of low fanout control sets

  • A design with a large number of control sets potentially can show lower device utilization (but not always)

  • Designs with a small number of control sets are preferable

    • The key is to evaluate slices that have unused registers
    • Try to build designs with common control sets (plan)


Control signals are the signals that are connected to the actual control ports on the register

  • Control signals are the signals that are connected to the actual control ports on the register

  • Clocks and asynchronous set/resets always become control signals

    • They cannot be moved to the datapath
  • Clock enables and synchronous set/resets sometimes become control signals (this is decided by the synthesis tool)

    • These control signals can be moved to the datapath (to a LUT input)
  • Asynchronous sets/resets have priority access to the control ports over synchronous sets/resets

    • Example: If an asynchronous reset and a synchronous reset are inferred on a single register
      • The asynchronous reset gets the port on the register
      • The synchronous reset gets a LUT input
      • There is no coding style or synthesis option that allows users to control when a LUT will be used for this purpose


Flip-flops with different control sets cannot be packed into the same slice

  • Flip-flops with different control sets cannot be packed into the same slice

  • Synchronous SR port can be converted to a flip-flop without SR using a LUT

    • This results in higher LUT utilization, but may result in lower overall slice utilization


CE port can be converted to a flip-flop without CE using a LUT and routing

  • CE port can be converted to a flip-flop without CE using a LUT and routing

    • This results in higher LUT utilization, but may result in lower overall slice utilization


The synthesis tool can be instructed to reduce the number of control sets in the design

  • The synthesis tool can be instructed to reduce the number of control sets in the design

    • Setting the value to “Auto” instructs the synthesis tool to reduce control sets by converting synchronous SR and CE to LUT implementations where appropriate


Instantiation of primitives and cores

  • Instantiation of primitives and cores

    • Gate-level connection of UNISIM and core primitives dictates control signal usage
    • Be aware that some IP does not necessarily follow the guidelines presented later
  • Synthesis optimization

    • Synthesis may choose to build a control signal for logic optimization
  • Physical synthesis, design hierarchy, and incremental design practices

    • Can change control sets from the original specifications (be careful)
    • Global or logic optimization may choose to build a control signal for logic optimization


Problem: Active-low control signals can produce sub-optimal results

  • Problem: Active-low control signals can produce sub-optimal results

  • This results in

    • Poor device utilization
      • More LUTs
      • Less dense slice packing
      • More routing resources necessary
    • Longer run times
    • Worse timing and power




Can these flip-flops be placed into the same slice? Note: All control signals drive the control port of the flip-flop

  • Can these flip-flops be placed into the same slice? Note: All control signals drive the control port of the flip-flop

    • Case 1
      • FF1: Clock, CE, Set
      • FF2: CLK, CE, Set
    • Case 2
      • FF1: CLK, CE, Reset
      • FF2: CLK, Reset
    • Case 3
      • FF1: CLK, CE, Reset
      • FF2: CLK, CE, not Reset
    • Case 4
      • FF1: CLK, CE, Reset
      • FF2: CLK, CE, Reset


Control Sets

  • Control Sets

  • Designing Resets

  • Other Reset Considerations

  • Summary



Control set restrictions can reduce design utilization

  • Control set restrictions can reduce design utilization

  • Your reset methodology can have a significant impact on your design efficiency

  • For designs that are not pushing the limits of your technology, it is recommended that synchronous resets be used for all storage elements

  • For more sophisticated designs, a mixed approach where only critical logic is explicitly synchronously reset, and all other logic relies on the GSR is recommended

  • Use asynchronous resets only when required



Software Manuals

  • Software Manuals

    • Start  Xilinx ISE Design Suite 13.1  ISE Design Tools  Documentation  Software Manuals
    • This includes the Synthesis & Simulation Design Guide
      • This guide has example inferences of many architectural resources
    • Xilinx Libraries Guide
  • Xilinx Education Services courses

    • www.support.xilinx.com  Products & Services  Xilinx Education Services
      • Xilinx tools and architecture courses
      • Hardware description language courses
      • Basic FPGA architecture, Basic HDL Coding Techniques, and other Free RELs!






After completing this module, you will be able to:

  • After completing this module, you will be able to:

  • Analyze different reset methodologies

  • Control the synthesis tool in these areas



Control Sets

  • Control Sets

  • Designing Resets

  • Other Reset Considerations

  • Summary



Global resets

  • Global resets

    • Sets all storage elements to a known state based on global criteria
      • Assertion of an external reset pin
      • Waiting for a PLL/MMCM to lock
  • Local resets

    • Internally generated signal that causes some storage elements to be forced to a known state
      • Example: The terminal count on a counter clearing existing conditions


Synchronous resets

  • Synchronous resets

    • A synchronous local reset is simply a part of regular logic
      • Any generated condition that causes one or more flip-flops to be returned to a fixed state can be viewed as a local synchronous reset
    • Synthesis tools are free to use the synchronous SR port as part of the implementation of normal functionality
  • Asynchronous resets

    • Using locally generated asynchronous resets is not recommended
      • Any glitch on the generated reset signal can cause unwanted clearing
      • A runt pulse on the generated reset signal can cause metastability


Based on a global criteria, all storage elements are set to a known state, using a synchronous SR port

  • Based on a global criteria, all storage elements are set to a known state, using a synchronous SR port

    • Each clock domain in the device uses a synchronized version of the global reset
  • Advantages

    • Simple to implement
    • “Foolproof”
    • Allows synthesis tools to perform control set reduction if necessary
  • Disadvantages

    • Will not work in situations where the clock is not guaranteed to be running
    • Uses substantial routing resources


Based on a global criteria, all storage elements are set to a known state, using an asynchronous SR port

  • Based on a global criteria, all storage elements are set to a known state, using an asynchronous SR port

    • Each clock domain in the device uses a synchronized version of the global reset
  • Advantages

    • Will work even if the clock is not present
    • Required for systems that need to generate valid outputs even when clock is not present
      • Input interfaces from “hot pluggable” devices
      • Interfaces using recovered clocks
  • Disadvantages

    • Cannot be control set reduced
    • Uses substantial routing resources


All new code should use synchronous resets when a reset is necessary

  • All new code should use synchronous resets when a reset is necessary

  • For existing code, you have three choices

    • Leave alone
      • Acknowledge the possible drawbacks of asynchronous resets
    • Use synthesis switch (dangerous!)
      • Not the same as changing to synchronous reset
      • This can make the synthesis result different from the behavioral simulation
    • Recommended: Manually change (or use a script) the asynchronous reset to synchronous


Routing can be considered one of the most valuable resources

  • Routing can be considered one of the most valuable resources

  • Resets compete for the same resources as the rest of the active signals of the design

    • Including timing-critical paths
    • More available routing gives the tools a better chance to meet your timing objectives


GSR is a special reset signal that is used to hold the design in a reset state while the FPGA is being configured

  • GSR is a special reset signal that is used to hold the design in a reset state while the FPGA is being configured

  • After the configuration is complete, the GSR is released and all of the flip-flops and other resources now possess the INIT value

    • The deassertion of GSR can take several clocks to affect all flip-flops in your design
    • The deassertion of GSR is asynchronous to all system clocks
  • The GSR can be asserted again from fabric logic by instantiating the STARTUPE2 module

    • Allows connection to the GSR net inside the FPGA


Resets are generally used to

  • Resets are generally used to

    • Initialize the design to a known state at power up
    • Control the starting up of the design after power up
  • The GSR ensures that all storage elements are at a known value after initialization

  • However, GSR deassertion is asynchronous and slow

    • Can cause metastability or illegal states in logic that starts autonomously
  • A mixed approach whereby the GSR is used to set the initial state and an explicit reset is used to manage the start up can be very efficient



Control Sets

  • Control Sets

  • Designing Resets

  • Other Reset Considerations

  • Summary



The DSP slice is more versatile than most realize

  • The DSP slice is more versatile than most realize

    • It can be used for multipliers, add/sub, MACC, counters (with programmable terminal count), comparators, shifters, multiplexer, pattern match, and many other logic functions
  • Each DSP slice effectively has more than 250 registers

    • None have an asynchronous reset
  • Using synchronous global resets allows the synthesis tool to use DSP slices more easily

    • Asynchronous reset methodologies will prevent the tools from using the storage resources in the DSP slices


Block RAMs obtain minimum clock-to-output time by using the output register

  • Block RAMs obtain minimum clock-to-output time by using the output register

    • Output registers only have synchronous resets
  • Unused block RAMs can be used for many alternative purposes

    • ROMs, large LUTs, complex logic, state machines, and deep-shift registers, for example
  • Using block RAMs for other purposes can free up hundreds of flip-flops

    • Using the block RAM in dual-port mode allows for greater utilization of this resource
  • Using synchronous global resets allows the synthesis tool to use block RAMs more easily

    • Asynchronous resets will prevent the tools from using the output registers on block RAMs


Synthesis can infer SRL-based shift registers

  • Synthesis can infer SRL-based shift registers

    • But only if no resets are used (otherwise flip-flops are wasted)
    • Or, the synthesis tool can emulate the reset
      • This uses extra resources and negatively impacts timing


Control Sets

  • Control Sets

  • Designing Resets

  • Other Reset Considerations

  • Summary



Control set restrictions can reduce design utilization

  • Control set restrictions can reduce design utilization

  • Your reset methodology can have a significant impact on your design efficiency

  • For designs that are not pushing the limits of your technology, it is recommended that synchronous resets be used for all storage elements

  • For more sophisticated designs, a mixed approach where only critical logic is explicitly synchronously reset, and all other logic relies on the GSR is recommended

  • Use asynchronous resets only when required

    • That is, when the clock may not be present


Software Manuals

  • Software Manuals

    • Start  Xilinx ISE Design Suite 13.1  ISE Design Tools  Documentation  Software Manuals
    • This includes the Synthesis & Simulation Design Guide
      • This guide has example inferences of many architectural resources
    • Xilinx Libraries Guide
      • FF functionality
  • Xilinx Education Services courses

    • www.support.xilinx.com  Products & Services  Xilinx Education Services
      • Xilinx tools and architecture courses
      • Hardware description language courses
      • Basic FPGA architecture, Basic HDL Coding Techniques, and other Free RELs!






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