Clock skew
Yüklə
3,61 Mb.
tarix
07.11.2018
ölçüsü
3,61 Mb.
#78586
Bu səhifədəki naviqasiya:
Variation of the pulse width
Only skew affects the race margin
2 Phase, with multiple conditional buffered clocks
Multiple clocks complicate race checking
Arbiter: Circuit to decide which of 2 events occurred first
Caveat: It is impossible to ensure correct operation
Clock skew
Clock skew
Spatial variation in temporally
equivalent clock edges
; deterministic + random,
tSK
Clock jitter
Temporal variations in consecutive edges of the clock signal; modulation + random noise
Cycle-to-cycle (short-term)
tJS
Long term
tJL
Variation
of the pulse width
Important for level sensitive clocking
Both skew and jitter affect
the effective cycle time
Both skew and jitter affect the effective cycle time
Only skew affects the race margin
2 Phase, with multiple
conditional buffered clocks
2 Phase, with multiple conditional buffered clocks
2.8 nF clock load
40 cm final driver width
Local clocks can be gated “off”
to save power
Reduced load/skew
Reduced thermal issues
Multiple clocks complicate race checking
Arbiter: Circuit to decide which of 2
events occurred first
Arbiter: Circuit to decide which of 2 events occurred first
Synchronizer: Arbiter with clock as one of the inputs
Problem: Circuit HAS to make a decision in limited time - which
decision is not important
Caveat: It is impossible to ensure correct operation
But, we can decrease the error probability at the expense of delay
Yüklə
3,61 Mb.
Dostları ilə paylaş:
Verilənlər bazası müəlliflik hüququ ilə müdafiə olunur ©genderi.org 2024
rəhbərliyinə müraciət
Ana səhifə
Psixologiya