Level-Sensitive Flip-Flop Level-sensitive flip-flop (also called a “latch”) “Q” changes whenever clock is “high”
Level-Sensitive Flip-Flop NMOS transistor often replaced with “transmission gate” “Transmission gate” includes both NMOS and PMOS transistors because NMOS good at passing “0” and PMOS good at passing “1”
Can connect two level-sensitive latches in Master-Slave configuration to form edge-triggered flip-flop Master latch “catches” value of “D” at “QM” when CLK is low Slave latch causes “Q” to change only at rising edge of CLK
Master-Slave Edge-Triggered Flip-Flop
More Efficient Master-Slave Edge-Triggered Flip-Flop Called a C2MOS (Clocked CMOS) design
From previous slides, you can see that it’s possible to build an edge-triggered flip-flop using just 8 transistors In a conventional “Digital Logic” course, transistor-level flip-flop designs are not usually taught Instead, flip-flop designs using “cross-coupled” logic gates are usually taught
RS-Latch as Cross-Coupled NOR Gates If R = 1, Q resets to 0 If S = 1, Q sets to 1 RS = 11 is not allowed because leads to oscillation
Level-Sensitive RS-Latch “Q” only changes when CLK is high (i.e. level-sensitive) When CLK is high, behavior same as RS latch
Level-Sensitive D-Latch Make level-sensitive D-latch from level-sensitive RS-latch by connecting S = D and R = not D Compared to transistor version
Master-Slave Edge-Triggered Flip-Flop Compared to transistor version
Alternative Edge-Triggered Flip-Flop
Same as RS-Latch except “toggle” on 11
Toggle Flip-Flop from D-Latch Toggles stored value if T = 1 when CLK is high
Dostları ilə paylaş: |