Max’s Chips and Dips



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Max’s Chips and Dips
As we all know, a Structured ASIC (known by some as a Platform ASIC) is one for which the transistors have already been fabricated along with most of the metallization layers. Every Structured ASIC architecture is different, but they are all typically based on a building block called a “tile” or “module.” This basic tile is replicated across the face of the device (along with blocks of memory and hard macros/IP), where each tile contains a mix of logic gates and/or multiplexers and/or lookup tables and/or register elements. The idea is that the user need only define very few metallization layers in order to complete the device (one architecture requires the user to define only a single via layer).
There are several advantages associated with Structured ASICs. First, the cost of the main portion of the design is born by the ASIC vendor and amortized across all of the customers using that particular technology. Second, the cost of creating just a few masks for only a small number of metallization layers means that the cost of the masks is very much reduced. Third, the fact that the bulk of the wafer has already been prefabricated means that you can obtain your prototype chips back in hand much faster. Also, the fact that these devices already have power grids and scan technology built in (many also have clock trees established) can significantly reduce the design cycle. Similarly, the fact that a lot of the signal integrity, power integrity, and related issues have already been addressed by the ASIC vendor can significantly reduce the time required to verify the device.
One consideration with these devices, however, is that you do need a synthesis solution that is geared towards handling a tile-based architecture, as opposed to more mainstream synthesis technologies that are tailored for use with fine-grained Standard Cell architectures. If fact, according to the folks at Synplicity, if one uses a generic (standard-cell ASIC-derived) physical synthesis solution to design your structured ASIC, then you can expect an average of three hand-off cycles to the ASIC vendor before your design is in a good enough state to be physically realized. In such a case, your Structured ASIC design will still end up taking around 2/3 the time of an equivalent full-up Standard Cell design.
As discussed in this issue’s technical article, Synplicity claim that – in order to achieve an optimum Structured ASIC design – one requires a physical synthesis tool that is tailored to the specific architecture of the device. Furthermore, using appropriate synthesis technology means that you typically need only perform a single hand-off to the ASIC vendor, thereby resulting in a Structured ASIC design cycle that is only around 1/3 of an equivalent full-up Standard Cell design!
Meanwhile (leaping from one topic to another with the agility of a mountain goat) the Unified Modeling Language (UML) is widely used in software engineering circles, but has not – thus far – attracted much attention from hardware designers. This state of affairs may change in the not-so-distant future, however, according to Wolfgang Muller as described in this issues Viewpoint column.
I very much hope you enjoy this issue of iDESIGN. Please feel free to email me with your thoughts and comments on the material presented here. Furthermore, if you have any ideas for technical articles or viewpoints for future issues of iDESIGN, please feel free to drop me a line at max@extensionmedia.com. Until next time, have a good one!
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