Introduction to Sigma Delta Converters P. V. Ananda Mohan

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Introduction to Sigma Delta Converters

  • P.V. Ananda Mohan

  • Electronics Corporation of India Limited,

  • Bangalore

How to reduce analog part?

  • Use Sigma-Delta Conversion

  • Front-end simple active RC Filter

  • SC/Gm-C Sigma- Delta converter working at high sampling frequency

  • Digital Decimation Filter using DSP

  • Scalable with digital technology

  • Only few OTAs or opamps, one comparator needed, MOS switches needed


What is sigma-delta conversion?

  • Similar to Delta Modulation but can code dc (i.e.Slowly varying signals)

  • Generates One bit output sequence

  • Output word is obtained from this sequence by finding the average using a decimator.

  • Also called “Pulse density modulation”

  • Also called “over-sampled A/D conversion”

  • High resolution up to 19 bits

  • Uses Oversampling and Noise shaping

  • Trades off accuracy in amplitude with accuracy in time


  • Analog part small area

  • Over sampling ratio typically 8 to 256.

  • Megahertz range up to 16 bits

  • Band-pass Sigma –delta solutions are also available.

First-Order Sigma Delta Modulator

Two-loop Sigma-delta modulator

  • Vo(z)=Vi(z)+en.(1-z-1)2 Second order noise shaping

Quantization noise of a linear A/D

  • Difference between staircase and linear is a triangular waveform.

Linear models for Analysis

  • Vo(z)= Vi(z)+en.(1-z-1)

  • Input low-pass and en high-pass transfer function; Shaping the Quantization noise!!!

Quantization noise for an A/D converter

Quantization noise of a Sigma delta converter

  • Noise shaping function (1-z-1) L

  • (1-z-1) L = (1-e-jωT) L = (e-jωT/2)L.(ejωT/2 -e-jωT/2)L

  • |(1-z-1) L | = | (ejωT/2 -e-jωT/2)L | = 2. Sin(πf/fs)

  • = (2 πf/fs)L

Candy’s Formula


  • (1-z-1)L has L zeros at dc

  • Signal and Quantization noise are treated differently.

  • Output word is obtained from a sequence of coarsely sampled input samples.

  • Analog part small area

  • Typical oversampling ratio 8 to 256.

  • For a Nyquist rate ADC DR2 = 3.22B-1

  • For Second Order Sigma delta Converter,

Decimation filter

  • Occupies large area and consumes power.

  • Linear Phase FIR filter can be used.

  • Comb filters preferred since the input data is one bit wide only.

  • Can Reduce sampling rate to four times the Nyquist rate.

  • Lth order Noise shaping function, L+1th order decimator is required.

Decimation filter

  • Local average can be computed efficiently by by a decimator.

  • Frequency response

Decimation filter

  • Decimation is reduction of sampling rate

  • Comb filters are used

  • Fixed coefficient FIR filters

  • One,Two or Three stages

  • Some designs use fixed coefficient IIR filters

  • Second order Sigma delta converter neds third-order decimator filter.

Decimation filter example

  • H(z) = (1-z-64)/(1-z-1)


  • Second order Decimator

  • H(z) = (1-z-64)2/(1-z-1)2

  • Third-Order Decimator

  • H(z) = (1-z-64)3/(1-z-1)3

  • Design is slightly involved-Three parallel processors

  • Coefficient generation is dynamic for both designs



  • Single stage Multiloop feedback

  • Multistage Noise Shaping (MASH)

  • Cascade Designs

  • Leslie-Singh Architecture

Fifth order single stage delta sigma modulator

Fifth-Order Leap-Frog Sigma-Delta Modulator

Single Loop Designs

  • No non linearity of DAC problems: only two levels one and zero.

  • Quantization noise power is very high and hence Need large over-sampling ratio

  • Single loop Sigma-delta modulators, gain progressively increases and overloads the comparator.

  • Delay also. Input change is felt after five stages.

  • High coefficient spread (large area)

Single Loop Designs

  • High coefficient sensitivity

  • Poor stability

  • All known digital filter structures cascade, direct form, Leap frog can be used.

  • Single loop Sigma delta modulators reduce integrator gin to achieve stability.

Multi stage noise shaping (MASH) Architecture


  • Leakage is proportional to 1/Av2

  • Leakage is proportional to σC2


  • Only last stage noise ideally remains.

  • Noise, distortion performance and Power dissipation dependent largely on the first stage leakage.

  • Digital Noise cancellation circuits.

  • Output is a word not a bit as in the case of Single stage 1 bit A/D based design.

  • Complicates digital filters following the Analog blocks.

  • Linear single bit Quantizer in the first stage

  • MASH needs to have low leakage, high opamp gain 90dB low voltage applications not easily realizable.


  • Leakage of Quantization noise from each stage is because of the finite gain of the OA

  • Capacitor mismatch also leads to leakage.

  • Many versions available called as 1-1-1,1-2-1, etc indicating the order of the loop in each stage.

  • Upto fifth order modulators built.

Leslie-Singh Architecture

Leslie-Singh Architecture

  • This Architecture avoids matching problems of DAC in first stage. Uses Two ADCs in effect.

Why Multi-bit Sigma delta converters?

  • SNR can be improved by using multi-bit without clocking fast, Candy’s formula

  • Problem of mismatch of resistors/capacitors occurs

  • Nonlinearity of DAC is troublesome

  • Number of bits increases exponentially the complexity (number of capacitors/resistors)

  • Typically restricted to 4 or 5 bits.

  • Can be used as single stage Multibit or one stage of MASH

Bandpass Sigma Delta

  • Advantage immune to 1/f noise

  • No need for matching I and Q signals

Band-Pass Sigma delta Modulator

  • H(z)=z-2 and N(z)=(1+z-2)2 Transmission zeroes at fs/4, Obtained by z-1 to –z-2 transformation.


Implementation Options

  • Switched Capacitor

  • OTA-C

  • Continuous-time

  • Combinations

SC Filters

SC solution

  • SC preferred because of accurate control of integrator gains.

  • Fully Differential design increases signal swing by two and dynamic range by 6dB.

  • Common mode signals such as supply lines, substrate are rejected

  • Charges injected by switches are cancelled.

  • First integrator is important regarding noise, linearity, settling behavior since second stage

  • Folded cascode Opamps recommended.

  • Nonidealities of comparator undergo noise shaping and hence not very critical.

  • Comparator can be simple.

  • Capacitors chosen based on noise requirements.

Typical Fully Differential SC integrator

Timing to avoid charge injection

Switch Implementation

  • Low ON resistance

  • Clock Feed-through (reduced by NMOS transistor shunted by PMOS transistor)

  • Effect is to cause dc offset due to aliasing!

Auto Zero-ed Integrator

  • Haug-Maloberti-Temes

  • Cancels noise, offset and finite gain effects

  • Output held over a clock period.

Switch Non-idealities

  • Fully-differential circuits recommended

  • Duplicated hardware; more area

  • Noise of switch due to ON resistance

  • kT/C noise, large capacitors need to be used for low noise, noise independent of Switch ON resistance Ron

  • Charging and discharging time dependent on

  • SC Sigma delta modulators OA of large bandwidth at least five times the sampling frequency and high gain are required.


  • Similar to OPAMPS but need logic level outputs

  • Input referred offset of MOS Opamps/comparators is quite high.

  • Offset compensation mandatory.

  • 10 bit ADC with 1V signal, accuracy of a comparator is 1mV. Thus, residual offset has to be much smaller than 1mV.

A MOS comparator Combining gain stage and latch

Typical Bipolar Comparator

  • Latch is a regenerative (positive feedback ) circuit

Flash Architectures for Multibit Sigma delta converters

  • Quite fast

  • Number of comparators needed exponentially increases with bit length.

  • Resistor ladders needed.

  • Usually 4 to 5 bit Flash A/D used to reduce area.

Flash architecture

Flash D/A converter Imperfections

  • Integral non-linearity

  • Differential non-linearity

  • Ac bowing due to input bias current drawn by comparators.

  • Comparator kickback noise during transit from latching to tracking

CT Sigma Delta Modulators

CT Sigma Delta Modulators

  • Help to increase the clock frequency

  • Consume less power

  • OSR needs to be reduced for high bandwidth applications.

  • No settling behavior problems.

  • Relaxed sampling networks

  • More sensitive to clock jitter

  • ADC jitter not much trouble

  • But DAC jitter troublesome. Since it is not noise shaped

  • Non-zero excess loop delay

CT Sigma Delta Modulators

  • Large RC time constant variation

  • Mismatch between analog noise shaping and digital noise shaping

  • CT Filters several alternative technologies abvailable:

  • Active RC linear, not tunable

  • Gm-C less power consumption,High frequency, tunable

  • MOSFET-C non-linearity, advantage of tunability

  • First stage is very important

  • Mixture of Active RC ,Gm-C used.

  • First stage Active RC for good linearity

  • Compensation capacitors not needed for Gm-C since integrator capacitor can compensate the OTA

Sigma delta DAC

  • More tolerant to component mismatch and circuit non-idealities

  • More digital

  • Keeping circuit noise low, and meeting linearity are the challenges.

Sigma Delta DAC

How to combat Nonlinearity of DAC?

  • Capacitors/Resistors do have mismatch. Randomize the mismatch.

  • In DWA, same set of DAC elements are used cyclically and repeatedly under the guide of a single pointer.

  • The element mismatch errors translate to tones at the DAC output when the DAC input has a periodic pattern.

  • DEM Logic must be optimized for low delay.


Power Dissipation

  • Settling performance of the Opamp decides gm.

  • Power dissipation is dependent on bias current which is decided by Gm.

General Guidelines

  • Stability (Overload)

  • Long strings of ones or zeroes are detected and reset is given to integrators to improve stability.

  • Stabilization techniques needed e.g. clamping of integrator outputs.

  • Extensive simulation needed e.g Matlab Sigma Delta Tool Box R.Schrier

  • Rules of Thumb

  • Maximum of Magnitude of H(z) shall be <1.5 (Lee’s rule)

  • More relaxed designs available now: Magnitude of H(z) up to 6.

  • Idle tones in band

General Guidelines

  • Thumb rule GB of OA > 2.5FS

  • Switch resistances can be as low as 150 Ohms.

  • Offset of Comparator <10mV

  • Hysteresis of comparator <20mV

  • Single stage modulators are quite tolerant of nonidealities

  • Instability means that large not necessarily unbounded states gives poor SNR compared to linear models.

  • Reducing OBG (Out of band gain) improves stability

  • Capacitors with low voltage coefficients ensure good linearity.

General Guidelines

  • OPamps with large dc gain in first stage.

  • Cancellation of even harmonics feasible by fully differential circuits

  • Top plates of capacitors to virtual grounds of Opamps

  • Full switches parallel NMOS and PMOS for input whereas only NMOS for those feeding virtual ground.

General Guidelines

  • Comparator metastability

  • Effect of clock jitter is independent of the order or structure of the modulator.

  • Clock A cos(ωot) becomes due to jitter A cos(ωo(t+αSin(ωt)).This adds to the input and sidebands are formed: ωo+ ω, and ωo- ω) of amplitude A α ωo/2

  • SNR is affected by A2 ωo2/2

Sigma Delta Frequency Synthesizer


  • More than 400 papers

  • IEEE press books

  • Simulation tools

  • Months of simulation may be needed to weed out problems.

  • Several solutions

  • Applications emerging for 802.11, Blue Tooth, CDMA/GSM/3G handsets




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