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to accommodate memory areas of 2 GiB some systems use variations of the memory map as shown in
table 5.
2.3.3 Memory Map in Systems That Need 2 GiB Memory Area
TABLE 5. Memory map accomodating 2 GiB main memory area
Base address
Description
0x00000000
RAM
0x80000000
Other
large area, for instance PCI bridge mapping PCI memory
0xC0000000
PROM / Memory mapped IO
0xD0000000
AHB/APB bridge
0xE0000000
Debug Support Unit register interface
0xFFF00000
AHB I/O area (if used by any core)
0xFFFFF000
Plug’n’play area (always located within AHB I/O area)
The memory map in table 5 allows a 2 GiB memory map in the address range 0x00000000 -
0x7FFFFFFF and is supported by the toolchains supplied by Cobham Gaisler by giving an extra
switch (see the toolchain and OS documentation for details). Note that the default start address for a
LEON processor is 0x0. If the memory map above is used, the reset start address should be changed
to 0xC0000000.
Existing LEON systems use variations of the above memory map. The main difficulties that can arise
from different memory maps is that the RAM and ROM areas may collide in linker scripts and boot
loaders. It is therefore recommended that RAM is always mapped at 0x40000000 or 0x00000000 and
that ROM (boot PROM area) is mapped at 0x00000000 or 0xC0000000.
Special switches may be required when building the application if RAM is mapped at 0x00000000.
See toolchain documentation for details.
2.3.4 AHB I/O Area and GRLIB Plug&Play Areas
It is recommended that the default addresses are used for AHB I/O areas (determined by generic on
AHBCTRL) and GRLIB AMBA plug&play areas (determined via generics on AHBCTRL and
APBCTRL). Software scanning routines will assume that one plug&play area is located at
0xFFFFF000.
It is possible to place the AHB I/O area and the AHB plug&play area so that it shadows another AHB
area. As an example a PCI core can be mapped at address 0xC0000000 - 0xFFFFFFFF while the
plug&play area is still reachable at offset 0xFFFFF000. While such memory maps are perfectly valid
and useful for many systems it generally not recommended to let the AHB I/O or plug&play area
shadow another area as software drivers may not recognize that some of the memory area assigned to
a core is essentially unreachable. When an AHB I/O area or the plug&play area shadows another
AHB slave it means that the AHB slave will not be selected when an access is made to the address
range occupied by AHB I/O or plug&play.
2.4
Interrupt Assignments
2.4.1 Overview
The LEON processor and interrupt controller provides 15 interrupt lines in the default configuration.
Interrupt 15 is non-maskable, which leaves 14 interrupts usable for peripheral cores. The multiproces-
sor interrupt controllers (IRQMP and IRQ(A)MP cores) can be extended to provide 16 additional
interrupts, called extended interrupts.
The GRLIB interrupt infrastructure allows any number of cores to share the same interrupt line. Note,
however, that sharing interrupts requires that the software drivers can handle shared interrupts. Also,
the time required to serve an interrupt request may be significantly prolonged if software needs to
check a large number of registers in order to determine if a peripheral asserted an interrupt.
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Some operating systems place additional constraints on interrupt assignments. The subsections below
describe the requirements of each OS. The basic rules to follow in order to be able to run the maxi-
mum amount of software can be summarized with:
1. If possible, have one dedicated interrupt for each interrupt source (no shared interrupts).
2. Configure the timer unit (GPTIMER) to have dedicated interrupts for each timer
3. Place the timer interrupts within the range 2 - 12
4. Leave interrupts lines 13 - 15 unused
The subsections below dealing with operating systems may become outdated due to changes in the
operating systems. If in doubt, please consult the OS documentation or contact Cobham Gaisler for
the latest information.
2.4.2 Linux 2.6 and later
Interrupt 15 is used for cross-calls. Interrupt 13 is the default selection for inter-processor-interrupts
(IPI). The interrupt line to be used for IPI can be selected when building the kernel and cannot be
shared with peripherals.
Linux also requires that the first timer on the general purpose timer unit (GPTIMER) has a dedicated
interrupt. For SMP operation the second timer must also have a dedicated interrupt line allocated.
2.4.3 RTEMS
RTEMS supports extended interrupts. Interrupt 14 is used for cross-CPU messaging in AMP systems.
This interrupt is defined in leon.h: LEON3_MP_IRQ, cannot be a shared interrupt and must be in the
range 1 .. 14.
RTEMS SMP is at the time of writing not finished and requirements are not known.
Timer 0 of GPTIMER 0 is the system clock timer, however RTEMS can be used without a timer.
There are two cases depending on which RTEMS distribution that is used:
Classical/official RTEMS BSP: GPTIMER0.timer0 must have separate IRQ and the interrupt must be
in the range 1 .. 14.
“Driver manager BSP” (RCC LEON3/4 BSP): Can handle both separate and shared IRQs on GPTI-
MER, interrupt can be in the range 1 .. 31 (no limitations).
2.4.4 VxWorks
VxWorks makes use of interrupt 14 for inter-processor-interrupts (IPI). This interrupt should not be
shared with peripherals.
2.5
Device Specific Identification
GRLIB systems have two identifiers in the system’s plug&play area that can be used to distinguish a
particular device: The GRLIB build ID and the GRLIB System Device ID. The GRLIB build ID is set
globally for the full library and the device ID is set per design via the AHBCTRL VHDL generic
devid (refer to the AHBCTRL section in GRLIB IP Core User’s Manual, grip.pdf). This VHDL
generic should be set to a unique value for all new designs. The file lib/grlib/amba/devices.vhd lists
device IDs, under the comment
grlib system device id’s, used for some existing designs. It is recom-
mended that customer designs use an ID larger than 16#0a00#. Please contact Cobham Gaisler sup-
port if you wish to have you device ID added to the listing in devices.vhd.
Communication interfaces may have additional vendor and device identifiers. This is, for instance,
the case for JTAG, PCI and USB. For the USB debug link it is recommended that users keep the
Cobham Gaisler IDs so that GRMON may properly detected the debug link. For all other identifiers
the implementers of a device should use their own IDs as assigned by the appropriate organisations.
Re-use of Cobham Gaisler’s vendor/manufacturer ID may prevent the device from fully functioning
together with software and debug tools.