# Jk and Master Slave Flip Flops

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 LECTURE X CH 5 CONTINUED The JK flip flop is unique in that it has two control inputs (J & K) but all possible inputs of J and K are possible. When J & K are both active, the value of Q will be complemented upon receipt of the CLK pulse. This is known as the Toggling mode. It can be used to divide the clock frequency by a factor of two if so desired. A commonly used JK flip-flop is the 74LS76 shown below. Note that triangles on the outside of the chip rectangle indicate active LO inputs and outputs. JK flip flops are considered to be universal because D flip flops can be made from them by inverting J into K. To make a toggling flip flop simply tie both J & K to HI. Consider the circuit shown below: Note that the inputs (J & K) are derived from outputs of other flip-flops. A timing problem would arise if the inputs are being latched into the flip flops at the same time that the outputs are changing. One could not predict the end results. The solution to this dilemma can be found in a special configuration of D and JK flip flops which latch the inputs present at J & K on the leading edge of the clock pulse but are not passed through to the outputs (Q and 'Q) until the trailing edge of the clock. This configuration of either D or JK flip flops is known as Master Slave flip flops. They are constructed from two similar flip flops connected together with the master accepting the inputs either on the rising edge of the clock pulse or while the clock is HI. The outputs of the master are then fed to the inputs of the slave. The clock input to the slave is the complement to the clock of the master. Hence, an entire clock pulse is required to accept new inputs and propagate them to the outputs. Here is an example of a JK Master Slave FF. Note that CLK, which goes directly into the Master FF, is inverted into the Slave FF. It takes one entire clock pulse to propagate the inputs presented at J and K to Q and 'Q. The leading edge triggers the Master and the trailing edge triggers the Slave. Metastability is a problem associated with all flip flops. It occurs when the inputs (D, JK, preset, etc) to a flip flop are not stable for a long enough period of time either before the triggering clock signal or after it or both. If inputs change as the input signals are propagating through the flip flop circuitry, unstable outputs may result. They may take longer than normal to settle to their desired states or might even oscillate for a period of time before finally settling down to the proper states. If these oscillating outputs are latched into the next stage of the circuit it is entirely possible that incorrect data will be accepted. Master slave type flip flops aid in the prevention of this occurring but are by no means are a concrete solution. It is, therefore, incumbent on the engineer to design circuits which comply with hold times specified in the data sheets for the devices being used. A few things to remember: 1) Latches are level triggered. 2) Flip Flops are edge triggered. 3) Master Slave flip flops require an entire clock pulse. 4) A transparent latch is one in which Q follows D (or S&R) for as long as the enable is acitve. 5) Data sheets for all Texas Instrument devices can be found at: http://www.ti.com/sc/docs/psheets/pids.htmYüklə 7,32 Kb.Dostları ilə paylaş:

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