Figure 4. Examples
of LEON clock gating
AHB CLK
GCLK
CLK
RESETN
DBGO.IDLE
D
Q
D
Q
LEON3/4 entity
AHB CLK
GCLK
CLK
RESETN
DSUO.PWD[n]
D
Q
LEON3/4 entity
DBGO.IPEND
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The processor should exit the power-down state when an interrupt become pending. The signal
DBGO.ipend will then go high when this happen, and should be used to re-enable the clock.
When the debug support unit (DSU3 or DSU4) is used, the DSUO.pwd signal should be used instead
of DBGO.idle. This will ensure that the clock also is re-enabled when the processor is switched from
power-down to debug state by the DSU. The DSUO.pwd is a vector with one power-down signal per
CPU (for SMP systems). DSUO.pwd takes DBGO.ipend into account, and no further gating or latch-
ing needs to be done of this signal. If cache snooping has been enabled, the continuous clock will
ensure that the snooping logic is activated when necessary and will keep the data cache synchronized
even when the processor clock is gated-off. In a multi-processor system, all processor except node 0
will enter power-down after reset and will allow immediate clock-gating without additional software
support.
Clock-tree routing must ensure that the continuous clock (CLK) and the gated clock (GCLK) are
phase-aligned. The template design leon3-clock-gate shows an example of a clock-gated system.
Please refer to the LEON signal descriptions in the GRLIB IP Core User’s Manual document for doc-
umentation on which processor clock inputs that are allowed to be gated-off. Please also see the docu-
mentation for the GRCLKGATE and GRCLKGATE2 IP cores in the same document.
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5
Debug communication links
5.1
Overview
GRLIB contains several debug communication link (DCL) controller cores. All DCL cores are con-
trolled over an external link to make accesses on an on-chip AHB bus. These communcation links can
be used by an external debug monitor to perform debugging operations on the system or by other
external devices that need direct memory access to the design.
5.2
Available debug link controllers
A debug communication link controller is an IP core that has that supports communication over an
external interface without on-chip software involvement. The IP core decodes incoming traffic and
translates the traffic to operations on the AMBA bus. The table below lists IP cores that can act as
debug communication link controllers.
TABLE 10. Debug Communication Link controllers
Interface
IP core
AMBA access
size supported
Notes
Serial UART
AHBUART
Word
Supported by GRMON
JTAG
AHBJTAG
Byte, Half-word,
Word
Supported by GRMON
Ethernet
GRETH /
GRETH_GBIT
Word
DCL functionality
is optional to include in
Ethernet controllers. Supported by
GRMON.
PCI
GRPCI / GRPCI2
Byte, Half-word,
Word
GRMON can make use of PCI target to
access system.
SpaceWire
RMAP
GRSPW
GRSPW2 /
GRSPWROUTER
Read: Byte,
Half-word,
Word
Write: Word
RMAP hardware handler is optional to
include in SpaceWire controllers. GRMON
can connect via GRESB Ethernet-to-Space-
Wire bridge. The controllers translate sub-
word read accesses to 32-bit read
operations.
USB
GRUSB_DCL
Word
Supported by GRMON
I2C
I2C2AHB
Byte, Half-word,
Word
Not supported by GRMON
SPI
SPI2AHB
Byte, Half-word,
Word
Not supported by GRMON
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6
Core specific design recommendations
6.1
Overview
The subsections below contain system design recommendations when using specific GRLIB cores.
6.2
AHB/AHB Bridges (AHB2AHB/AHBBRIDGE/GRIOMMU)
The AHB/AHB bridges can be of high value when partitioning the system into several clock domains
or when there is a need to separate bus traffic. The use of a bridge will result in increased latencies
when accesses need to traverse over the bridge.
For bi-directional bridge configurations the designer needs to be aware that collisions (attempts to tra-
verse the bridge both ways simultaneously) will mean that the access on the slave bridge will be
aborted and then re-attempted. This situation can potentially lead to starvation and deadlocks.
When instantiating the bridge with a prefetch buffer the buffer should be scaled so that it does not
prefetch unnecessarily large amounts of data. If the master(s) traversing the bridge have a maximum
burst length of eight words, then the bridge’s prefetch buffer should not be larger than eight words.
6.3
SVGA Controller (SVGACTRL)
The SVGA controller can consume a significant amount of the available bus bandwidth. Even if cal-
culations show that there is plenty of bandwidth available, the inclusion of SVGACTRL may add bus
access latencies that significantly impact computational performance. For design that include a
SVGA controller it is recommended to place the SVGA controller on a separate bus with a dedicated
frame buffer memory.