Synthesizing and Testing leon on adm-xrc anup Gangwar

Synthesizing and Testing LEON on ADM-XRC

• Anup Gangwar

• Embedded Systems Group

• Department of Computer Science & Engineering

• IIT Delhi

Introduction

• What is LEON?

• A Sparc V8 compliant soft processor core
• No support for paging
• Has been synthesized and tested on many FPGA platforms
• Mainly written by Jiri Gaisler at European Space Agency
• Supporting toolkit (compiler, assembler, simulator) available
• RTEMS successfully ported to LEON with support for n/w interface

• How is this relevant to our work?

• Real performance/cost nos. give valuable feedback to our tools
• Prototyping adds credibility to our work
• System design experience lets us identify new problems
• Working demonstrations help motivate new people

The LEON Processor Architecture

LEON Development Tools Suite

Motorola S-Records Format

ADM-XRC Architecture

ADM-XRC Software API

• Supported platforms are GNU-Linux and Windows NT

• API Supports:

• Functions for configuring the Virtex device over PCI
• DMA mode for data transfer from/to PLX-9080
• Both master/slave mode supported for PLX-9080

• Examples demonstrate:

• Simple PCI interface
• RAM interface with address space segregation
• DMA Master and slave interfaces
• External I/O interfaces

Why it took so long?

• Inability to comprehend the problem properly

• Improper documentation of ZBT memory interface

• Improper methodology for prototyping and testing

• Synthesis being used as testing vehicle which is incorrect
• After thorough simulation synthesis should be a one-shot process unless the synthesis tools are buggy

• External H/W interface was incorrect

• Unnecessary additional logic inversion
• Position of Rx and Tx in 9-pin and 25-pin connectors is interchanged

• LEON and memory address lines were not properly mapped

• LEON address lines select individual bytes!
• Memory word is 32 bits here hence LEON A[1:0] need to be left free

Galvantech ZBT SRAM Interface Signals

ZBT SRAM Read Timing Diagram

ZBT SRAM Write Timing Diagram

LEON SRAM Read Timing Diagram

LEON SRAM Write Timing Diagram

External Hardware Interface

• Why is external hardware circuitry needed?

• Virtex SelectIOTM supports PCI3.3, LVTTL etc. logic levels
• RS-232C voltage conversion required for TxD and RxD pins

• Choices for interface chips

• Motorola MC1488/1489
• Require dual supply, +5V, ±12V
• Better noise immunity but bigger circuitry
• LVTTL to RS232C and RS232C to LVTTL requires two chips
• Maxim Max232
• Single power supply, +5V
• Each chip contains two RS232C to LVTTL and two LVTTL to RS232C converters
• Lesser noise immunity but more compact circuitry

H/W Interface Board Layout

Boot Configuration

From Here:

• Small Scope Projects:

• Try various hardware synthesis configurations for LEON
• Build S/W and H/W estimator models for LEON

• Medium Scope Projects:

• Build a host of coprocessors for LEON
• Test some PCI cards with LEON-PCI
• Port some real applications to LEON-RTEMS
• Build Ethernet interface for LEON (RTEMS support is already present)

• Large Scope Projects:

• Extend LEON configuration for multiprocessors
• Customize RTEMS for a particular application/LEON configuration

Acknowledgements

• Main ideas, motivation and support

• Prof. M. Balakrishnan and Prof. Anshul Kumar

• Co-Proc interface, Local Bus interface, Bugs in memory interface

• Amarjeet Singh

• Debugging, Memory interface, External RS-232C hardware interface circuitry

• Amit Aggarwal, Puneet Wadhawan

Thank You