Computer Peripherals

0.3.
Computer I/O Architecture
Before proceeding with the study of computer peripherals, a brief review of the
architecture of the computer, the requirements of interface design, and the structure of computer
buses will be given.
[TC1]
The digital computer normally consists of the central processing unit (CPU), memory,
input devices, output devices, and storage devices as shown in Fig. 1.1. Interconnecting these
components are the address, data and control buses. It is seen that each of the peripheral devices
is connected to CPU through the interface unit. These interface units generally comprise the
following:
(i)
Transmit and receive data registers/buffer: As the CPU and the peripheral operate
asynchronously at different speeds, these registers and buffers (FIFO) are use to hold
and transfer data to and from the peripheral device. The length of these registers is
normally the same as the data-word length of the peripheral device.
(ii)
Control registers: One or more control registers are used to capture and store the
command received from the CPU. With programmable devices, mode registers are used
to set the mode of operation of the device.
(iii)
A status register: Each bit of the status register is used to indicate individual status
conditions to the CPU. Sometimes the CPU also writes the status register. In this case
the peripheral reads it to determine the status of the processor.
(iv)
An address decoder: Irrespective of whether the device is interfaced using memory-
mapped or I/O-port techniques, the device will still have to decode the address
information from the CPU to determine whether it should respond. Again for
programmable devices, a series of addresses is decoded.
CPU
Input
Devices
Devices
Output
Storage
Devices
Memory
Interface
Interface
Interface
Local Bus
Bus system
Other
Bridge