Computer Peripherals

0.5.3.
Direct Memory Access (DMA)
Interrupts provide fast response to a peripheral device, but the servicing of the interrupt is
performed in software. Sometimes I/O transfers need to occur faster than interrupts can manage,
such as with disk I/O, high-speed graphics, or interfacing to a Local Area Network (LAN). The
servicing previously carried out by software can be performed faster if it is done by specialised
hardware. Such a dedicated controller is designed to perform one specific task only, namely the
high-speed transfer of data between the I/O device and memory (and vice versa), but bypassing
the CPU. Hence the technique is referred to as Direct Memory Access (DMA).
With DMA, the device actually takes control of the system bus for the time required to
transfer the data, then hands back the bus to the CPU upon completion. Most harddisk
controller uses a DMA Controller (DMAC) for data transfers between disk and memory. The
disk is connected to a peripheral controller which communicates to the DMAC via the Transfer
Request and Transmit Acknowledge handshake lines. The DMAC in turn interfaces to the CPU
via the Bus Request, Bus Acknowledge and Transfer Complete lines.
It is important to realise that the DMAC itself is accessed by the CPU as a typical I/O
device, with its own unique port ID, vector and interrupt priority. However, once the DMAC
has been granted the bus in 'burst' mode, it cannot be interrupted by the CPU (in this sense the
DMAC has priority over the processor). With 'interleaved' or 'cycle steal' DMA, the DMAC and
CPU share alternate bus cycles.
DMA transfers are inherently faster than either interrupts or polling, since they bypass
altogether the imbedded instruction fetch-decode-execute cycles of the CPU. Rather than
fetching instructions sequentially from memory, a DMAC has inbuilt (firmware) instructions.
Moreover, these instructions can be executed concurrently, for example, transferring data at the
same time as decrementing a byte counter.