0.6.
Summary
In
this introductory chapter, we revised interfacing of Input/Output (I/O) devices to a
CPU. In current development, this is usually facilitated by the use of user-programmable
peripheral support chips. Such peripheral chips are connected
to the CPU in master-slave
configuration, with their onboard command and status registers accessible via the system bus.
More recent peripheral support chips comprise dedicated I/O processors, some of which employ
a
coprocessor philosophy, which leads to concurrent operation of the peripheral chip and the
CPU.
Memory-mapped and ported I/O schemes were compared and contrasted, and the
advantages and disadvantages of each mentioned.
The need for both hardware and software buffering between CPU
and peripheral device
was highlighted - the former for matching electrical signal levels, and the latter for the
temporary storage of data until the CPU (and/or peripheral) can deal with it.
The basic I/O
techniques of software polling, interrupts and Direct Memory Address
(DMA)
were introduced, and their respective advantages and disadvantages pointed out.
0.7.Reading Guides
WILKINSON & HORROCKS, Sections 2.2, 2.4
FULCHER, Sections 1.2, 1.5, 1.6, 3.4
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