Opus manual
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- Bu səhifədəki naviqasiya:
- Create a new working library
- Create the schematic of the inverter
- Plotting the Schematic of the Inverter
- Create a symbol for the inverter
- Spice simulation with eldoD of Mentor Graphics
- Exercise using the cursors and the slope function
- Create the layout of the inverter
- Comparison Layout Versus Schematic (LVS)
- Simulation of the extracted netlist
LINUX PrimerBasic LINUX Instructions(Linux instructions have to be typed in a console (’shell’) window. All instructions have to be terminated with ls list: lists elements of a directory by their names ls –l list long: detailed listing of a directory: access right, owner, length, date, name ls –a list all: list including the hidden files too (beginning with '.') ls –al list all long: detailed long listing of all files ls –lt long listing ordered by the time of generation mkdir dirname make directory named dirname rmdir dirname remove (delete) the directory dirname (only if the directory is empty) rm filename remove (delete) the file filename du disk usage lists the complete hierarchy downwards with size (1 kByte blocks) cd subdir change directory to subdir cd change directory to the home directory of the user kate filename opens the file filename for editing (new file if filename does not exist) About LINUXAfter logging in LINUX comes up with the panel bar at the bottom and with the first of three different desktops activated. Then with a left click at the Konsole icon you have to open a Konsole shell window. This window can be your workhorse as long as you are working direct with LINUX. When a new shell opens you are at the highest level of your user account. This is your Home Directory, which can be referred to by the tilde '~' character. The directory where you are can be represented by the dot '.', the preceding higher level directory by two dots '..'. You can move up and down among the directories with the cd command. Typing ls -al you will find among others the file .bashrc which contains settings for the operating system. (If it does not yet exist you may open a new one with the editor.) The following two lines show examples for your own usage: alias lth='ls -lt | head' If you type lth then LINUX will produce a time-ordered list of the ten most recent files - an alias which can be favourably used for checking the recent changes in the directory. alias ed='kate' Instead of kate xxx you can simply type ed xxx and the editor will start with the file xxx. An ampersand '&' after the filename will make the editor start as a stand-alone process so that your window remains free for other work. Any change in .bashrc will be effective only after your next logging-in. HINT: If you copy ~gaertner/.bashrc to your home directory then you will have these and several other features in your account:
When already copied, you can add other aliases for your personal usage, too. OPUS PrimerThe objective of this part is to teach a quick and easy start into the Cadence system without going into details. Going through this primer a simple inverter will be designed making the following steps: schematic entry, drawing a symbol, simulating the circuit with eldoD of Mentor Graphics (Spice), designing the silicon layout, design rule check (DRC), circuit extraction,
comparison layout versus schematic (LVS), simulation of the extracted netlist. This primer alone can bring you to the above-mentioned results. It is recommended, however, to first read the introductory chapter of the manual, because the basic background knowledge acquired there will make it easier to follow and understand the procedures. LINUX preparationOpen a subdirectory for the priming activities. Type mkdir ams37. ams37 will be the home directory for OPUS in your account. All OPUS activities will take place inside this directory. Starting OPUSThe very first start only initializes the design environment. Left click at the icon IC Design Framework on the desktop. A new LINUX shell comes up and asks for the design-directory of OPUS. Type ams37 In return OPUS offers the available technologies. AMS 0.35 um CMOS (c35b3) has to be used, so type 1 
Fig. 1 Command Interpreter window OPUS goes on. The Log window appears with some logging messages, then it changes to the msfb-Log window which is called the Command Interpreter Window (CIW) because it can accept commands which you type in (Fig. 1.). The library manager window, too, starts automatically, but here you have to exit OPUS by clicking at msfb:File->Exit. So the initialization is done. When you start again, clicking at the icon, then OPUS won’t ask any more question and you can go on using the library manager window. The library manager window can be used for opening existing libraries or cells or creating new ones. The left column of the library manager window is a list of the current (accessible) libraries. Among these PRIMLIB contains the transistors you will need for the inverter. Left click at PRIMLIB. The middle column shows the elements of PRIMLIB. Left click at nmos4. This is the basic n-MOS transistor. In the third, rightmost column you can see several views of nmos4. Of these you will need the symbol view for the schematic and the layout view for building the layout. 
Fig. 2 Library Manager window Create a new working libraryBefore building the schematic you have to create a working library. In the Library Manager left click at File->New->Library. A dialog box appears, asking for the place and name of the new library (Fig. 3.). 
Fig. 3 New Library dialog box Leave the directory at the default, and enter a name for your working library where you are going to design the inverter, such as, for instance, mylib. Left click the OK button. Cadence now creates a new subdirectory named mylib in its home directory (ams37). A new window will appear asking information about the technology file. The second option, Attach to an existing techfile, will be used, click at it. Then click on the OK button. A small dialog box appears asking for the existing techfile (Fig.4.). Left click at the Technology Library button. A list of possible choices pops up. Click at TECH_C35B3 and then OK. Your library is created now and you should be able to locate the new library mylib in your Library Manager. 
Fig. 4 Choosing the technology for the project Create the schematic of the inverterIn the Library Manager left click on File->New->Cell view. The Create New File form appears (Fig. 5.). 
Fig. 5 Specifying the name and view of a new cell Type a meaningful name in the Cell Name block, such as e.g. myinv. In the View Name block type schematic or from the Tool menu choose Composer-Schematic and the View Name block will be automatically filled. Set the library for the would-be cell mylib. Left click the OK button. The Virtuoso Schematic Editing window should show up (Fig. 6:). 
Fig. 6 Schematic Editing window Left click Virtuoso Schematic Editing:Add->Instance. The Add Instance dialog box appears (Fig. 7.). Type PRIMLIB in the Library field. To choose a four-terminal NMOS transistor type nmos4 in the Cell field and symbol in the View field. Note that you can use the Browse button in order to browse through the libraries and find the cell you want. Generally, typing in known names is faster. When OPUS learns that you want to place an instance of a transistor then it adds fields to the box for the parameters of the transistor, already containing default values. Just change the Width to 2u (two microns).
Move the cursor into the editing window. Notice that there is an nmos transistor there instead of the normal cursor. Position it where you want to put the transistor, and place it by a left click. Having placed the first component, change the name of the transistor in the dialog box to pmos4 and the width to 5u. Now you have prepared the second half of the inverter and you should place the pmos transistor somewhere over the nmos device so that they can be connected by a straight line. If you type Left click Add->Pin. The Add Pin dialog box appears (Fig. 8. next page). Type in out in the Pin Names field for the pins of the inverter. Set the Direction to input. (Note that the order of the pins is not important. You may even place one pin at a time and repeat the procedure.) Move the cursor into the editing window. A pin symbol appears with a small square at the right edge. Place it left of the transistors in the middle with a left click. In the dialog box in disappears from the pin-list, only out remains. Change the Direction to output. In the editing window an output pin symbol appears, having a small square at the left edge. Place it right of the transistors in the middle with a left click. In a simple case power supply pins (vss, vdd) should be added, too. However, in an IC power supply is provided in a centralized way. In the schematics it is done by the global nodes gnd! and vdd! while in the layout there are the power rails which do it. Global node names end with an exclamation point (!). Contact to the global nodes gnd! and vdd! is established by placing instances (small symbols) of the cells ground and vdd. They are stored in the library analogLib. The procedure is the same as for the transistors. Invoke the Add Instance window with a left click at Add->Instance. Select with the browser the library analogLib and then the cells ground and vdd. Place them underneath and over the transistors, respectively. 
Fig. 8 Add Pin dialog box with pin specification Now we'll add the wires to make things work. Click Editing:Add->Wire. Notice that as you get closer to one pin than to another (including those on devices), a small diamond will show up inside of or around that pin. That is where you can click to connect a wire. To begin with, left click the diamond at the pin of the symbol vdd, then left click on the source terminal of the PMOS transistor. The first connection is finished. Now left click on the drain terminal of the PMOS transistor and then on that of the NMOS transistor. Follow that with a wire from the source of the NMOS transistor to the pin of gnd. Make one more vertical connection between the gates of both transistors. Now, left click on the diamond in the in pin. Move the cursor horizontal to the wire you connected the two gates together with. A diamond will form around the cursor, as long as it is on the wire. Left click. You have just connected the input to the gates of both transistors. Repeat the procedure from the output pin to the wire connecting the drains of both transistors.
What remains is connecting the bulk (body) terminals of the transistors. Left click on the bulk terminal of the PMOS transistor. Move the cursor a little right, and left click. The wire will turn here. Now move upwards halfway to vdd. Left click again and move to the wire connecting the drain and vdd. Connect the bulk of the NMOS transistor to vss in a similar manner. If you happen to put a wire where you don't want it to go, you can delete it by left clicking Editing:Edit->Delete and then left click on the object you want to delete (wire, pin, component, etc.). Once you have done editing, left click the check mark (√) icon on the left side of the screen. This will check your work for connection errors and will save your cell (more exactly: its schematic view!) in the library. You can accomplish the same by left clicking Editing: Design->Check and save. Fig. 9 shows what the complete schematic should look like. This very simple schematic of an inverter will likely be flawless but in more complex designs OPUS may find errors which will be highlighted after the check (blinking). In such a case you may click Editing:Check->Find Marker. Then the Find Marker window opens (Fig. 10.) and you will find there the list of the highlighted errors and warnings with the reasons stated.
If the paper box of the plotter is empty and you happen to want to plot on a sheet of paper which only has one free (empty) side, then make sure that the empty side of the paper looks downwards. Create a symbol for the inverterThe symbol editor lets you create a "black box" description of a cell using labels, pins, shapes, notes and a selection box. Symbols enable you to introduce hierarchy into your designs. In the Library Manager left click on File->New->Cell view. The Create New File form appears. Ensure that the library name is mylib. Fill in the cell name myinv and the view name symbol. Left click the OK button. The Virtuoso Symbol Editing window should show up. (Fig. 12. on the next page shows it with the would-be result.). 
Fig. 11 Sending a circuit diagram to the plotter Start drawing with a triangle to represent the inverter body. Left click Editing:Add->Shape->Polygon. To draw a polygon, left click at a start point and then click at the corners of the shape you want to create. To finish the polygon, click again on the start point. Since we have an inverter, we need an "inverter-like" triangle. As to the size of the symbol: Note that there are small white dots in the black background of the editing window. If you carefully move the cursor then you will find that its movement is quantized, between two dots it can make 16 small jumps. The triangle should occupy about a "4 by 4 jump" area. The inverter needs a negation circle at the sideways corner of the triangle, so left click Editing:Add->Shape->Circle. Left click at the would-be center of the circle and then at the corner of the triangle. A radius of "one jump" is recommended. Next you have to create pins for the symbol. It is similar to creating pins in the schematic but the pins look different. They consist of a little red dot and of a piece of line. The dot is the pin itself. The line binds it to the body of the symbol, its length can be adjusted.
Left click Editing:Add->Pin. The Add Pin box shows up. Type the pin names, they must exactly match those of the schematic: in out. Do not forget to set the correct direction for the pins before placing them. Moving the cursor to the editing window the pin appears. With left clicks on Add Pin:Rotate you can change the direction of the connecting line. Place the pins so that the red dots are at the far end and the connecting lines join the body of the symbol. At last the position of the pin names have to be adjusted so that the symbol looks nice. Moving the cursor to a name a yellow box appears around it. Now you can left drag the name to its final position. 
Fig. 13 Adding a label to the symbol Next we want to add two labels to the symbol. Left click Editing:Add->Label. The Add Symbol Label dialog box should appear (Fig. 13.). The usual default setting is [@instanceName], Label Choice: instance label, Label Type: NLPLabel. With this setting you only have to move the cursor to the editing window. The label [@instanceName] at once appears and you can place it with a left click. The next label is the name of the cell. Fill into the label field myinv and choose Label Type normalLabel. Place it again with a left click. The last thing to add is a selection box. This will tell the software how much of the symbol is actually used. Left click Editing:Add->Selection Box. Left click the Automatic button. The selection box will be automatically drawn. The symbol is now finished and you can save it by left clicking Editing:Design->Save. If the pin names and attributes do not match those of the schematic then warnings show up and you have to correct the mismatch. Simulate the schematicThe functionality of an integrated circuit is verified by simulation. For a simulation the following things are needed:
The netlist can be extracted from the schematic, it is usually done automatically. Power and input signals are provided by generators. They might be directly added to the schematic but this method is not recommended. Instead, a test bench should be built which takes the cell to be tested as an instance and provides the necessary simulation environment. This has several advantages. The cell remains unchanged and independent of the simulation. It is quite easy to simulate and compare different versions and views of the cell, you only have to specify a cell and a view in the test bench. Create a test benchTo keep things apart, test benches are usually built in a separate library. For this reason open a new directory testlib just the same way you created mylib for the schematic of the inverter (page 4). Then open a new cell with schematic view, e.g. test_inv. The first element of the testbench is the cell to be tested. Left click Editing:Add->Instance. A dialog box comes up and you can either type Library mylib, Cell myinv, or you can browse through the libraries and specify it there. Place the symbol of the inverter in the middle of the screen. 
Fig. 14 Specifying a pulse generator Left click Add->Instance->Browse. Select the generator vdc from the library analogLib. Set the field DC Voltage to 5 V. This will be the power supply, place it far left. Now you might go on browsing for other components but in this case it can be done easier, too. Change the name of the cell to vpulse and close it with a Now left click Add->Wire or type simply <w>. Make the common ground net connecting the lower terminals of the three components. Next connect vpulse to the input and the capacitor to the output of the inverter. Place one more piece of wire to the output and add an output pin named out (left click Add->Pin, etc.). Left click Editing:Add->Wire Name. Fill in Names: uin. Move the cursor to the wire connecting vpulse and the input of the inverter and place the name onto it. In the next step you have to provide for the global vdd!. It is done by placing a vdd symbol from the library analogLib and connecting it to the positive terminal of the vdc generator. It is important for the simulator that the ground net has the name gnd! and the internal node number zero. This can be achieved by placing one more component. Left click again Editing:Add->Instance and fill in: analogLib for the Library and gnd for Cell name. Place the ground symbol underneath and connect it to the ground net by a piece of wire. If you happen to get very unusual and unlikely voltage values resulting from the simulation then check if this condition is fulfilled! The test bench is complete, left click Design->Check and Save (Fig. 15.). 
Fig. 15 Testbench – test environment for the inverter Spice simulation with eldoD of Mentor GraphicsWe are going to analyze the DC transfer characteristics and the transient behavior of the inverter. Open the schematic test_inv in the library testlib. Left click Tools->Analog Environment. The Virtuoso Analog Design Environment window opens (Fig. 16). In the status bar (second from top) the default simulator Spectre is displayed. In order to change the simulator left click Setup->Simulator/Directory/Host. The Choosing Simulator window opens. The simulator box displays Spectre. Left click on the box and select eldoD, then click OK (Fig. 17.). Check the change in the status bar of the Design Environment window. 
Fig. 16 Analog Environment -- main control panel Left click Analyses->Choose. The Choosing Analyses dialog box comes up. Now specify the simulation. Select Analysis: dc (Fig. 18, next page), switch off Print Operating Point, select Sweep Variable: Source (1). Next you specify Sweep Range. Fill in Start 0 and Stop 5 and By 0.01. Left click at the box Select S1. Switch over to the schematic and select the the sweeping source by clicking at the pulse generator drv at the input of the inverter. Then switch back to the Choosing Analyses dialog box. In the 1stSource field /drv should appear. See if the Enabled checkbox is switched on and click at Apply. In the same window you can specify the transient simulation as well. Select tran and set From Time 0, To Time 25n. Switch on the Enabled checkbox and click OK. In the Analyses field of the Analog Environment window the specified data appear. 
Fig. 17 Choosing the eldoD simulator 
Fig. 18 Selecting simulation parameters Next we want to select which results should be plotted. Left click on Analog Design Environment:Outputs->To be Plotted->Select on Schematic. Click on the wire between your pulse generator and the in pin of your inverter bearing the label input. Then click on the wire between the out pin of the inverter and the out pin of the test bench. Both wires should change color indicating that these voltages will be plotted. Note: if you want to select a current to be plotted then click on the square of a symbol where the current is flowing through. There will be a circle around the square node indicating that a current is selected. Try it with the vss and vdd terminals of the inverter. A second click on the same square cancels the selection. Now you are ready to run the simulation. Left click Simulation->Run or click on the green traffic light icon on the right side of the Analog Design Environment window. If a dialog box appears now requiring your decision whether some simulation results should be saved then your answer must be Yes! The simulation runs and after a while the results will be plotted in two different ways. The first is the Waveform Window of Opus, you should ignore it by simply closing. The second one is the window of the display program EZwave which we are going to use. Extend this window to the whole screen and arrange the results neatly side by side.
The results are plotted in the same coordinate-system. You can separate them by a right click inside the window and activate Split in the pop-up menu (Fig. 19). On the right side of the curve you see the colour-code and the name of the curve. To unite curves you can select the curve by left-click at its name and then left-drag the highlighted name to another one. To finish the simulation exit eldoD Spice. Left click on Analog Design Environment: Session->Quit. Remember NOT to save the current state. If you choose to save then several hundreds of megabytes will be used in order to save your last simulation. Note: the specified simulations in the Analyses field can be enabled and disabled one by one. To do so select the simulation by a left click and then left click Analog Design Environment:Analyses-> Enable or Disable (or even Delete). Exercise using the cursors and the slope functionRead the section Simulation: EZwave Window, Cursors and Slope (page 35) and do the following exercise. Start the DC Sweep simulation of the inverter again, with the curves out and uin. When the EZwave window opens with the curves make it to form a large square on the screen. Now find three characteristic points of the output curve of the inverter:
Fig. 20 Finding voltage gain and rise time Create the layout of the inverterThe tool for layout creation is called VIRTUOSO. Select mylib in the Library Manager and then myinv in mylib. In the View column the already existing views Schematic and Symbol appear. Left click Library Manager:File->New->Cell View. The Create New File dialog box shows up with myinv in the Cell Name field. Left click on Virtuoso in the popup menu of the tool selecting block. layout will be automatically filled in for View Name. Having clicked at the OK button two windows will appear, the Virtuoso Layout Editing window and the LSW (Layer Select) window. Adjust the layout editing window beside LSW to the rest of the screen (Fig 21. shows both windows). The LSW window is the one you will use to choose the different layers for the IC design. It contains a list of the possible layers. Each entry is divided in three categories which are color, abbreviated name and purpose. Color shows the appearance of the layer in the layout. The abbreviation is the official name of the layer for Virtuoso, it can appear in messages, etc. The purpose can be drw for drawing and pin for pin, you will almost always need drw. A layer can be activated for editing by a left click in the list. It gets a black frame as highlighting and will be displayed at the uppermost part of the LSW window (current entry for shape processing commands). 
Fig. 21 Layout editing windows showing the target layout cell The four buttons in the next line control the visibility and selectability of all shape elements: AV = all visible NV = none visible AS = all selectable NS = none selectable. When switching on and off, the elements in the list will be grayed. The visibility of single layers can be controlled by right click, the selectability by middle click. Some general information to the editing window: The buttons on the left side speak for themselves. For zoom-in a rectangle can be drawn by right drag. You can return to the previous view by depressing When the mouse is inside the editing window then the X and Y coordinate values of the cursor are displayed between the title bar and the menu bar. Notice the dX and dY items, too. When creating shapes, these show distances relative to the last click. If you make a mistake at any time you can left click on Editing:Edit->Undo. You can refresh the drawing by a left click on Editing:Window->Redraw. Before starting prepare the battlefield for your work. Left click Editing:Options->Display. The Display Options dialog box opens containing usual default settings. In the Display Controls block switch on the buttons Pin Names, Nets and Instance Pins. In the Grid Controls block set both X and Y Snap Spacing to 0.05. For Display levels fill in To 9. Underneath switch on the button Cellview and click on the button Save To and then OK. This means that these settings will be stored in the cell view file, so that they will be automatically set whenever the cell view will be opened (Fig. 22, next page). One more setting: Left click Editing:Options->Layout Editor. The Layout Editor Options dialog box opens containing usual default settings (Fig. 23, next page). In the Gravity Controls block set Aperture to 0.1 and then left click OK. Now it is time to start building the layout of your inverter myinv. The main elements are the transistors which are quite complex structures consisting of pieces of different layers. You might draw these pieces one by one, carefully complying with all design rules.
However, you can take advantage of the library where "prefabricated" parametrizable transistor instances can be found. They contain all details in compliance with the design rules, you only have to taylor them to your need (i.e. length and width). Left click Editing:Create->Instance. The Create Instance dialog box opens (Fig. 24, next page). If you exactly know it then you may fill in Library and Cell Name of the cell you need. If not, click on the Browse button and find and select it in the library. Now we need (in accordance with the schematic) nmos4 from the library PRIMLIB. As soon as Virtuoso notices that a parametrizable instance has been specified, it extends the Create Instance dialog box for specifying the size of the transistor. Fill in width=2u, length is defaulted to 0.35u. Activate the button Substrate Contact. Shifting the cursor to the editing window the contour of the transistor appears. You can recognize the gate as a narrow horizontal strip. With three right clicks you can turn it 3x90 degree so that the gate is vertical and the substrate contact is on the left side. Place the transistor in this position.
Repeat the procedure with a pmos4 transistor. Set the width to 5u and switch on the substrate contact. Again, with three right click bring it into a favorable position. It has a similar structure to the NMOS transistor but it is surrounded by an N-well (the layer is called NTUB). Place it above the NMOS transistor so that
The transistors of the inverter have to be connected with each other: gate with gate and drain with drain. Zoom in so that these areas can well be seen and processed. In the LSW window left click on the layer MET1. Then left click Editing:Create->Rectangle. With two left clicks or one left drag make a MET1 box between the drains with the same width as those. Now change the entry layer to POLY1 and repeat the action for the gate terminals. 
Fig. 25 Placement of the transistors of the inverter Check the correct placement of the connecting elements. In the LSW window left click at NV (nothing visible except the previously selected POLY1) and then middle click at the layer MET1. Then make a left click at Editing:Window->Redraw. Everything disappears from the screen except the selected POLY1 and MET1. They must form a continuous long bar each. In case of misplacement you may delete and repeat, or you may use the editing commands move or stretch. Afterwards click at LSW:AV and then at Editing:Window->Redraw. Next you have to provide power supply. This inverter is supposed to be part of a standard cell design so you have to comply with the supposed standard power supply structure
Set the entry layer to MET1. Left click Editing:Create->Rectangle. Make a 6 um wide and 3 um high box (dX=6, dY=3). Left click Editing:Move. Depress the special-key The VDD rail has to be positioned carefully. Left click Editing: Create Ruler (or simply depress The power rails being there, connect the source and bulk contact areas to them. Contact and a piece of MET1 are already there, you only have to place two appropriate (1.6u wide) MET1 boxes, one from the NMOS to the GND-rail, and another from the PMOS to the VDD-rail.
Now an input terminal pin has to be prepared on MET1. Left click Create->Contact. The Create Contact dialog box opens. Set Contact Type to P1_C. Width and Length is automatically at 0.4 by 0.4 um. Click at Hide and place the contact box at the left side of the poly line connecting the gates. The contact comes with a small (minimum) MET1 box around the contact hole itself. There must be a minimum distance of 0.45 um from the MET1 box of the contact to the MET1 line connecting the drains. For the pin add a piece of MET1 line, 0.7 um wide, about 1 um long, extending the MET1 square to the left. F  ig. 27 Dialog box for layout pins The placement of the pins follows. Left click Editing:Create->Pin. The Create Symbolic Pin dialog box appears (Fig. 27, previous page). Select Pin Type MET1_T and enter Pin Width 0.5. Switch on the button Display Pin Name. (Important! If you forget it now then the only way to fix it later is to delete the pin and repeat the placement.) Enter the names of the pins: gnd! vdd! in out. I/O Type should be defaulted to input/Output. Bring the cursor to the middle of the GND rail and make a left click. The pin will be placed but the pin name, too, appears and has to be placed with another left click. Similarly place now vdd!. Then change the I/O Type to Input in the Create Symbolic Pin dialog box and place the pin in and, eventually, change the Pin Type to Output and place the pin out. They must lie inside the respective MET1 boxes. For correct simulation the power pins have to be furnished with Net Expression Properties. For this action select the gnd! pin. If you find some difficulty in selecting it, open the Display Options dialog box (left click Editing:Options->Display) and switch off the display of Nets. So the small square of the pin disappears, but if you move the cursor to its (empty) place then it appears as a yellow dashed line. Now type <q> and the Edit Instance Properties dialog box opens. Check the Connectivity button. In the property sheet you can read gnd! as the Terminal Name (see Fig. 27a). Fill in Net Expression Property=gnd and its Default value = gnd! then click at OK. Repeat the same procedure for the vdd! pin, too, filling in vdd and vdd!.
The last layer to add is CELBOX (cell-box). Make it the entry layer and draw a rectangle around the cell so that everything is comprised. Do it carefully so that the box exactly coincides with the power rails. The origin (0,0) of the cell has to be adjusted to the lower left corner of the cell box. Left click Editing:Edit->Other->Move Origin. Now the coordinate axes move together with the cursor. Bring the origin to the lower left corner and place it with a left click. Click on the Save button! You hope the layout is finished. DRC and LVS will tell you if it is really complete.
Design Rule Check (DRC)(DRC is the most important examination the layout is subjected to. Safe chip operation can only be guaranteed if there is no violation. As long as there is even only one single violation, the production of the chip must not be started.) DRC can be started from the layout editor window. Left click Editing:Verify->DRC. The DRC dialog box opens (Fig. 28.). 
Fig. 28 Window for starting DRC Check the following settings: Checking Method: flat Checking Limit: full Switch Names: empty -- no entry! Rules File: divaDRC.rul Rules Library: TECH_C35B3 Machine: local By clicking on Apply or OK the DRC could be started now and you would get at least several violations about minimum densities which are irrelevant in this case. Therefore, they have to be excluded from the checking activities. Left click DRC:Set Switches. The Set Switches box pops up (Fig. 29). Left click on no_coverage then left click OK. The selected option appears in the field Switch Names. Now you can start DRC with Apply or OK. If it is free of errors then save it! 
Fig. 29 Switch for excluding the coverage function If DRC happens to find errors then they will be reported in the Command Interpreter Window (CIW) but you can analyze them one by one. Left click Editing:Verify->Markers->Find. The Find Marker dialog box appears. Switch on the Zoom To Markers button and click on Next. The editing window will zoom to the marker and the marker text message box explains the rule violation to you so that you can correct it. You have to iterate with error corrections until you reach zero error. Layout extractionDRC guarantees only the manufacturability of the structures on the chip. However, the functionality of the structures has to be checked, too. For this purpose the structures will be analyzed and a netlist will be constructed this is called extraction. Left click Editing:Verify->Extract. The Extractor dialog box appears (Fig. 30). 
Fig. 30 Dialog box for starting the layout extraction Check the default settings:
Start the extraction by a click on Apply or OK. In the CIW window you get a long report which should end with Total errors found: 0. If there are errors such as structures which cannot be interpreted as a correct device then these will be highlighted and you can do find and explain markers similarly to the case with DRC errors. Afterwards you can check in the library manager whether the new view extracted for the cell myinv has appeared. Comparison Layout Versus Schematic (LVS)Open the extracted view of myinv. What you see is quite similar to the layout. If you zoom in you can find the schematic symbols of recognized and extracted circuit elements somewhere at the edge of the corresponding layout pieces (Fig. 31, next page). The question is if the realized circuit extracted from the layout is identical to the schematic which was the basis of its design. Left click Editing:Verify->LVS. The LVS dialog box opens (Fig. 32, next page) with data for the extracted netlist already filled in. Either you fill in data for the schematic (Library, Cell, Schematic) or click on the browser button and select the schematic from the library by the mouse. Check other default data:
At LVS Options switch off Rewiring. Left click at the Run button. The comparison starts. After a while the Analysis Job Succeeded message box appears and notifies you about success or failure of the LVS. Click on OK or Cancel and afterwards on LVS:Output. 
Fig. 31 Extracted transistor in the layout 
Fig. 32 Window for starting LVS A quite long report of the LVS job appears with statistics and some details about possible faults. If you can find the line The net-lists match that means full success for you -- supposed that the schematic is correct (Fig. 33.). 
Fig. 33 LVS report file indicating “happy end” Simulation of the extracted netlistThe last step is to check that not only the extracted netlist matches the schematic but also the simulation results are (nearly) identical. They should be identical but the stray capacitance of the wiring may influence the transient response. After simulating the schematic we will change the content of the inverter symbol in the testbench. (If you newly start the Analog Design Environment then you first must switch over to the eldoD simulator.) Left click on Analog Design Environment: Setup->Environment. The Environment Options dialog box opens (Fig. 34.). Change the block Switch View List to eldoD cmos_sch extracted schematic and then click on OK. 
Fig. 34 Switching to layout simulation Now you can start the simulation and check whether it brings the expected results. Yüklə 138,01 Kb. Dostları ilə paylaş:
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