Opus manual

Layout

MOS Transistor Structures

AMS 5.1.41 C35B3 is a 0,35 μm n-well process, based on a lightly doped p (π) type substrate. Here NMOS transistors can directly be constructed in the substrate while for PMOS transistors a lightly doped n (ν) type well has to be formed as a container represented by the layer NTUB. In case of an NMOS transistor source and drain are formed by two n+ zones with the poly gate in-between. The PMOS transistor has a complementary structure in that it is built in the n-well with p+ zones instead of n+. The size of the transistor is determined by the thin oxide, represented by the layer DIF and the poly stripe (POLY1) crossing it. The type of the transistor is determined by the type of diffusion. For the PMOS transistor acceptors are driven into the n-well, represented by the layer PPLUS. For NMOS transistors donors are needed, represented by the layer NPLUS. (Fig. 40.)



Fig. 40 Complementary MOS transistors, N and P

The bulk of the NMOS transistor is the substrate itself, which can be accessed by a substrate contact. An ohmic contact to the π type substrate is made by DIF and PPLUS layers. For a PMOS transistor the bulk is the n-well to which the ohmic contact can be made by DIF and NPLUS layers. The appropriate diffusions only prepare the place for the contacts, the opening of the thick oxide occurs by placing a contact (CONT) layer and then MET1 upon them.

Building Different MOS Transistor Instances

There are several (many) design rules to comply with when building transistors. In order to make it easier for the designer OPUS offers ready-made parametrizable transistors complying with all design rules. Designers are encouraged to use these rather than construct transistors layer by layer. In addition, the parameters enable the construction of a wide variety of transistors, flexibly tailoring them for individual needs. The transistors are stored in cells and are placed into your layout as instances. Here follow some examples.

Using the layout editor Virtuoso left click at Create->Instance. Enter Library=PRIMLIB, Cell=nmos4 and View=layout and close it with a tabulator. The Create Instance window will be extended and all the adjustable parameters of the selected cell (in this case the transistor nmos4) appear. (See Fig. 24, page 18.) Some parameters which cannot be modified are grayed. In the following the parameter data fields are explained. Following the Library, Cell and View fields the Names field accepts identifier(s) for the instance(s) to be placed. You may give meaningful unique names to the instances, if you don't then OPUS automatically generates a meaningless but unique character string for each instance.

Multiple placement of a cell is also possible. The data group Mosaic specifies the matrix of the instances: number of rows, columns and the spatial frequency Delta Y and Delta X of the elements of the matrix. Default values are the single placement (1 row and 1 column) and the width and height of the cell for the Delta's.

In the field Magnification a scaling factor may be given but the default value 1 usually suffices.

The next group concerns the position of the cell to be placed, they have to be clicked at if needed. Rotate means turning 90 degree clockwise. After the fourth click it returns to the original position. Sideways and Upside Down perform mirroring at a vertical and horizontal axis, respectively. These transformations can be applied independently.

The next group of data concerns the size of the transistor (Fig. 41, next page). Width is the total width while Width stripe means the width of the elementary transistor in case of a multi-finger structure. For the latter the Number of gates has to be given, too. These data are not independent, OPUS expects

Width = Width stripe * Number of gates

The program automatically corrects Width and Width stripe depending upon Number of gates.

MOS transistor shape: There is a choice of structures with the possibilities of normal and snake. Normal is the basic rectangular form which can be flexibly tailored. Snake is a special form used mainly for power transistors.

Top or Bottom Contact: They can be switched on and off upon need. In complex transistor circuits some connections may be realized on diffusion level. Accordingly, an external contact is not always needed, e.g. see the series transistors of a NAND gate.



Fig. 41 Parameters for size and form of the transistor

Join Gates or all drains or all sources: the choice is right, left and no. If the gates of an interdigit transistor are not joined (connected with each other) then you get a number of transistors connected parallel if sources and drains are joined or else in series if sources and drains are not joined.

Substrate contact: if there are several transistors in one well then one substrate contact is enough, the other transistors can be generated without substrate contact.

The flexibility of transistor generation is illustrated by the example of Fig. 42. showing two triple transistor groups of a NAND3 gate, the N-transistors being connected in series and the P-transistors being connected parallel

Fig. 42 Composite transistors

Three cascaded N-transistors can be created out of three single nmos4 transistors with the following properties (left to right, each one is normal):

1. 
   Rotate, Sideways, width=1 μm, length=0,35 μm, No. of gates=1, only bottom contact, Substrate contact on.
   
2. 
   Rotate, width=1 μm, length=0,35 μm, No. of gates=1, all contacts off.
   
3. 
   Just as previously with the bottom contact on.
   

These three elements are shown separately as they were generated. Then with careful Move actions they can be shifted together. The distance between the poly gates should be minimal. You can easily find out the minimum in that you shift them very near to each other and then perform a DRC. The error message which you get will state the acceptable minimum distance. Then you have to correct the position of the elements accordingly. The picture shows also the edited triple transistor.

The case of the P-transistors is different. They are generated as one three-digit pmos4 transistor with the following properties:

Rotate, width=3 μm, width stripe=1 μm, length=0,35 μm, No. of gates=3, normal, both top and bottom contacts, Join NO gates, Substrate contact on, Join all drains on, Join all sources on.

With these two transistor groups a NAND3 gate is half ready: the sources have to be connected to the appropriate power supply, the drains connected with each other produce the output, and each poly gate of the N-transistors connected with one gate of the P-transistors make the inputs.

Ready-made Contacts and Vias

Under Create Instance you may select the library TECH_C35B3. Here you will find minimum size contact structures for N and P diffusion as well as for poly: ND_C, PD_C, P1_C. They contain the minimum size squares of all layers involved. The default setting is a single contact but you may specify a matrix by setting its rows and columns. (If low contact impedance is needed then you have to place a matrix of small contacts rather than a single big one.) Similarly, there is a via structure for the transition between the metal layers MET1 and MET2, it is called VIA1_C. Stacked vias (via direct over a contact) are not allowed.

Pins

The pins of the cell are connected to the wiring network of the chip. They are usually placed on a net inside the cell, between the power rails. They may be placed on POLY1, MET1 or MET2. A general rule for pins is that they have to be available by a vertical MET2 wire in both directions up- and downward. It is rather the exception than the rule if the pin is only available on POLY1 from the routing channel. If the pins happen to be on POLY1 or MET1 then space must be left for vias descending from MET2 down to the layer of the pin. If cells contain elementary hierarchical subcells, their interconnections are considered as cell-internal. Their pins may (should!) be connected in the cell (possibly not in the routing channel). Consequently, they need not be available by a vertical MET2 wire. Just a simple example: making an AND gate using a NAND and an inverter cell. The output of the NAND should be directly connected to the input of the inverter, possibly between the power rails, because it is an internal net of the cell.

How To Make Pin Names Visible?

Display of pin names can be switched on and off generally. Left click Virtuoso Editing:Options->Display. The Display Options window (see Fig. 22, page 17) opens with the checkbox Pin Names (among several others). However, if you forgot to check the Display Pin Name box on the window Create Symbolic Pin (see Fig. 27, page 20) when the pin was placed then you must delete the pin and place it again with the box Display Pin Name checked.

Design Rules

Each silicon technology has its design rules which state what can and cannot be built, usually in terms of minimum distances. These data are proprietary and usually not public. Whether a layout design complies with these rules is checked by the DRC (design rule check) procedure. The design rules are stored in some technology files. For educational purposes there is a set of design rules installed in OPUS which does not correspond to any proprietary technology but they have to be complied with when students do their practical design activities. The most important elements of these rules are listed in Table 1 (next page).

DRC without checking percentage of coverages

Complying with minimum distances is not the only condition for successful silicon technology. The design rules also contain minimum conditions for the whole area covered by different layers on the complete chip. These conditions, however, need not be checked when designing a cell. In order to avoid meaningless error messages you can switch off these checks. In the DRC window left click at Set Switches. The Set Switches window opens. Left click at no_coverage (see Fig. 29, page 22) and then OK. If you start DRC now then it will not produce the unnecessary error messages in connection with too low coverages.

Table 1. The most important DRC rules (listed in μm) NOT VALID!

Minimal: Width Spacing Notch

NTUB 3 3 3

DIFF 0,3 0,6 0,6

POLY1 0,35 0,45 0,45

PPLUS/NPLUS 1,6 1,6 1,6

POLY2 0,65 0,5 0,5

CONT 1 1,2 1,2

MET1 0,5 0,45* 0,45

VIA 1,2 1,6 1,6

MET2 0,6 0,5** 0,5

PAD 15 25 25

* If the MET1 is wide (width>10μm) then 0,8

** If the MET2 is wide (width >10μm) then 0,8

Minimum spacing between different layers:

NTUB – DIFF 3

DIFF – PPLUS 0,35

CONT in MET1 – POLY1 0,8

CONT in POLY2 – POLY1 1,6

POLY1 – VIA 1

POLY2 – VIA 1,2

CONT – VIA 1,2

POLY1 – POLY2 1,4

POLY1 – DIFF 0,4

POLY2 – DIFF 1,2

Overhang in transistors:

POLY1 over DIFF 0,6

DIFF over POLY1 1,4

Spacing inside the surrounding layer (clearence)

CONT in DIFF 0,5

CONT in POLY1 0,4

CONT in POLY2 0,6

CONT in MET1 0,2

VIA in MET1 0,2

VIA in MET2 0,3

DIFF in NTUB 3