Opus manual

Simulation

EZwave Window

EZwave is a really handy, easily usable waveform display tool. Its usage is quite self-explaining. If you do not specify any signals to be plotted in the Analog Design Environment window, then the simulation will be executed and waveform data of all nets will be stored in a .wdb file. However, no EZwave window will be opened automatically. In such a case you can open an EZwave window with a left click at Analog Design Environment:MGC Sim->EZwave New Window. The window opens and on the left you can see the signal-pane. Here the available signals can be displayed in a hierarchical style, just like a file system. You can select signal names with mouse-clicks and send them to the waveform-pane to be displayed (Fig. 43.). The curves can easily be zoomed in and out. They can be selected by left click. When you make a right click there are different functions in different pop-up menus depending upon if you directly click at a curve or in-between. On the right of the curves the color-code and the name of the curves are displayed. The names can be selected and by vertical dragging the respective curves can be united in one common coordinate system, or separated in different coordinate systems.



Fig. 43 EZwave window

EZwave Cursors and Slope

To read the values of curves cursors can be added to the waweform-pane. After a left click at EZwave:Cursor->Add a highlighted vertical line appears just over the y axis of the coordinate system together with two textboxes displaying the x and y values. The cursor can be shifted to and fro by left drags and the values follow the position. Having two cursors the x-difference is also displayed.

Another useful feature is the slope-tool. With a right click at a curve you can choose the Add Slope entry of the pop-up menu. At that very point a tangential will be drawn to the curve and in a textbox the slope will be displayed (Fig. 44, next page).

Parametric Simulation (Transistor Characteristics)

It is possible to run a multiple simulation and display the results in a common diagram. The runs differ in that a parameter of the circuit is changed and so the influence of the parameter upon the behavior of the system can be investigated. This is the parametric simulation which needs some preparation. There is no restriction in the type of the parameter. It may be the temperature, the gate width of a transistor or the value of a resistor, etc. The simulation will be executed with double sweeping and you will get a group of parametrized curves.



Fig. 44 Slope and cursor in the waveform window

As a simple illustration of the parametric simulation the output characteristics of an NMOS transistor will be drawn by the simulator. For this purpose a very simple circuit is needed. Take an instance of the transistor nmos4 from the library PRIMLIB and two instances of the voltage source vdc from the library AnalogLib. Connect the voltage sources to the input and output ports of the transistor G-S and D-S, respectively. Don't forget to place a gnd symbol to the source node (Fig. 45.).

Fig. 45 Schematics for drawing the characteristics

Select the drain voltage source and type . The property sheet of the voltage source opens. Fill in Instance Name = VDS. Enter <5> in the value box of the DC voltage and click at Apply. Then select the gate voltage generator, the property sheet changes to its properties. Now enter the name VGS and again 5 Volt, and click OK. Click Add->Wire Name, enter into the dialog box ugs and uds, then click at the respective wires so they will have these labels. The complete schematic diagram is shown on Fig. 45 and is ready to be simulated.

Fig. 46 Switching over to the eldoD simulator

The simulation is prepared as usual: Tools->Analog Environment, switch over to the eldoD simulator (shown on Fig. 46.) and then Analyses->Choose. For output characteristic curves DC analysis has to be chosen with two Sources. The first source is /VDS, Start=0, Stop=5 and By=0.01. This will be simulated and displayed as a curve. The second source is the parameter changing in comparatively large steps: /VGS, Start=0, Stop=5 and By=1. Check the Enabled box and click OK (Fig. 47.).

Fig. 47 Setting the parameters of the double-sweep simulation

Then click at Outputs->To be Plotted->Select on Schematic and select the drain current by clicking at the drain pin of the transistor. In the list of the selected outputs the drain current appears with yes no no in the columns Plot, Save and March. In order to have the data saved click Outputs->Setup. The Setting Outputs window opens with the table of outputs (Fig. 48.). Select the only line of the table by clicking at the signal name I0/D and change the no Save entry to yes by checking the box Will Be Saved and then click at OK. The window closes and a yes appears under Save in the table of outputs.

Fig. 48 Setting Outputs window

Now you can start the simulation and after a while the results will be displayed in an EZwave window, shown in Fig. 49.

Fig. 49 Output characteristics of an NMOS transistor

Guidelines for the Practical Work

Schematics

Try to draw a circuit diagram which is easy to read and understand. If there are subunits with clearly defined functions then introduce hierarchy even if the block is used only once in the circuit - it enhances readability.

Circuit diagrams of standard cells have to contain the instances of gnd and vdd from the library PRIMLIB in order to establish contact to the power supply by using the global node names gnd! and vdd!. Signals are connected to the external world by means of pins. Do not forget to specify the correct direction input or output. Set inputOutput for bidirectional or power pins! On several occasions they are checked and you may get warnings or even error messages. Similarly, be consequent in using pin names because some operations are case sensitive.

It is important to have meaningful pin names which give the reader information about the role and function of the pin. Pins must have names - internal nodes (nets), too, should be given meaningful names (Composer-Schematic Editing:Add->Wire Name). Having automatically assigned net names like NET_19, NET_34, etc. is confusing while names like ENAB_COUNT or LOAD_REG or COUNT5<4:0> help to follow the function of the circuit or to evaluate simulation results.

Use always four-terminal transistors such as nmos4 or pmos4 where bulk electrodes are separately connected.

Layout

Strategy for Building Standard Cells

The basic property of standard cells is their common height or, more precisely, their common power rail structure. In the case of the student laboratory projects this consists of two 3 μm wide horizontal MET1 stripes running parallel at a medium distance of 25 μm, hence their internal distance is 22 μm. The lower one is the ground (global node gnd!) and the upper one is the power rail (global node vdd!). The components are placed in-between while the outer space is reserved as wiring channel.

The placement of the global pins gnd! and vdd! needs some additional setting. Their properties have to be additionally edited. After selecting them and depressing the Edit Instance Properties dialog box opens. Here Connectivity has to be checked. Terminal Name is displayed (gnd! or vdd!). Net Expression Property and its Default value have to be defined as gnd and gnd! as well as vdd and vdd! respectively.

If this property is missing then everything will run correctly with the only exception of the simulation of the extracted netlist. The LVS will not be influenced, but the simulator will not be able to connect the power supply to the power rails of the layout and, therefore, the circuit will not function at all. All voltages will be in the order of 100mV.

The great majority of the components are transistors. P-channel transistors are usually placed near the power rail. N-channel transistors are usually placed near the ground. Other components have to be placed so that they should allow for easy wiring.

Common N-well for the P-channel transistors in digital cells: Because the bulk electrodes of all transistors are connected to the power rail, they may be placed into one common N-well which is laying along the power rail. Consequently, the P-transistors do not have to have substrate contacts one by one. One bulk (substrate) contact for 50-60 μm cell width suffices.

Substrate contact of N-channel transistors: N-transistors do not have separate wells because they can be placed into the P-type substrate. However, the substrate, which is their common bulk electrode, has to be connected to the ground rail. The frequency of the substrate contacts is similar to that of the well contacts: once in every 50-60 μm cell width.

Transfer gates are different in that both their source and drain carry signals. The N-transistor is “floating” in the surrounding substrate and should have no substrate contact at all. Its bulk is connected to the ground. The P-transistor must have a separate n-well which is connected to vdd! by the well contact.

Wiring levels and directions: Beside two metal layers MET1 and MET2 poly-silicon (POLY1), too, can also be used for making connections, favorably between gate electrodes which are themselves poly. However, they are restricted for cell-internal, and possibly short, connections because of their high resistivity compared with the metal leads.

General rules for the direction of MET1 and MET2 are horizontal and vertical, respectively. However, for cell wiring these general rules have to be compromised with two other points of view:

• 
  Try to make as much of the connections between the power rails as possible, using mainly MET1 and, if necessary, POLY1.
  
• 
  Keep the cell for vertical MET2 as transparent as possible. Accordingly, if MET2 is used in the cell then it should be either vertical or only quite short if it must be laid horizontally.
  

If it is still not possible to make the connection between the power rails then horizontal MET1 stripes can be laid direct underneath the ground or above the power rail, and the points to be connected should be connected to this "external" lead by vertical MET2 stripes.

It is warmly recommended not to begin with the building of the cell without prior placement and routing considerations. The best way to do it is to draw simplified stick diagrams on paper. This way you can select proper places for the transistors which enable easy routing – saving by this act tedious rearrangements in the layout.

Making LVS: Frequently Encountered Problems

LVS is a very difficult job for the computer and, therefore, it has to be done by following very strict rules. Even slight differences between the original netlist and the extracted one can disturb the matching process, causing seemingly strange error messages. Errors reported in the report file (see Fig. 33.) can be inspected by a left click at LVS:Output (see Fig. 32.).

There is always a last remedy of making “human LVS” studying the netlists and searching for differences, although it is mostly quite tiresome. In OPUS LVS creates a subdirectory LVS. In this subdirectory there are further subdirectories layout and schematic, each containing the respective netlist under the name netlist. The netlists are textfiles. They can be inspected by means of the texteditor of LINUX (kate <filename>) but they must not be changed. The syntax is not described here, however, it is quite self-explaining, (similar to Spice).

LVS maps the elements of a layout (components and interconnections) to the corresponding elements of the schematic. It begins at the terminals (pins) of the netlist but it can use node names too, which are on the highest hierarchical level (those on lower levels are irrelevant). Consequently, both pin names and highest level node names must exactly match in layout and schematic, higher/lower case included. Ground and power rails must have the names gnd! and vdd! respectively.

Instance names are irrelevant for matching but component cell names also have to match  library name included. The components in the library have different views such as symbol for the schematic, layout for the layout and lvs for the extracted netlist. LVS can only match the views of the same cell. If unmatched components remain in the error list of LVS then you should carefully check the cell names of those components in the netlists.

If the difference in the netlist of the schematic and the layout has been found then the usual way of correction is to change the component in the schematic to that type which the extractor extracted from the layout. It is worth while mentioning that the extractor does its job upon the basis of the extractor rules file. This file contains a program for analyzing and recognizing layout structures and map them into lvs views of cells. The difference of the netlist of the schematic and the layout might be eliminated by adjusting the rules file - but the rules file is attached to a given technology and is not available for modification.

Inputs of logic gates are logically equivalent. It is irrelevant, which input of a 4-input AND gate the output of another cell is driving. But not so for LVS. The LVS of OPUS has analog character and expects exactly the same circuit structure in layout as well as in schematic. It happens quite often that the failure of LVS is caused by such a logically correct mismatch. The remedy again: rearrange in the schematic the logically equivalent input connections of the multi-input gate according to the layout

Documentation

Data Sheets

The cell design is only complete with data sheets containing all available data of the cell. Of course it is the specification which is the basis of the data sheets, for it was the basis of the design work, too. (Some data of the specification may have been modified in the course of the iterative design steps.) But there are other properties of the circuit which have not been specified. For instance: sensitivity of some parameters from supply voltage and/or temperature. Such data are only by-products of the design "as they are", but they, too, have to be determined by additional simulations and documented.

Digital Library Cells

The data sheet of a digital cell usually consists of:

• 
  a header containing the name of the library and of the cell,
  
• 
  the function of the cell,
  
• 
  the schematic icon of the cell,
  
• 
  the truth table of the cell,
  
• 
  input capacitances,
  
• 
  timing data,
  
• 
  date and name of the author.
  

These items are self-explaining, only the timing data need a detailed description. In case of direct propagation like in combinational circuits the propagation delay in both directions l-h and h-l have to be specified, as a function of the capacitive load. This means a function of y=mx+b style where b is the delay without load and x is the capacitive load:

t_d = t_d0 + m * C_L

This is an approximation of the reality which is widely used for gate level simulation of complex digital circuits. In such a case a gate is modeled with its logic function, its input capacitances and with the timing data t_d0 and m. When the simulator reads the netlist, for each gate it adds up the input capacitances of all connected gates and computes the actual delay for each gate. Similarly, rise time and fall time also have to be specified in the same style. According to their definition, delays are measured at 50% of the signal change while rise and fall times from 10% to 90%.

All these data may slightly depend on the slope of the input signal. Therefore, to be realistic, it is recommended to choose the slope of the input signal near that of the output signal with a load which is equal to the input capacitance of the given circuit.

t_d0 and m can be determined by running two simulations of the cell: one without load and one with a typical medium-sized load such as ca. 300 fF. (It can be a typical example for the parametric simulation with C_load as parameter having the values of 0 and 300 fF.)

For data inputs of sequential circuits set-up and hold times have to be specified. Parametric simulation can help here even more than in determining the delay data. Both set-up and hold time can be determined by choosing the pulse delay of the input generator as parameter and making small steps such as 50 or 100 psec.

Fig. 50. shows a simple sample of a data sheet of an inverter.


DEPARTMENT OF ELECTRON DEVICES
0.35 μm CMOS Static Cells

Cell Group Function Cell Name

Input Capacitance [fF]: IN = 120

Version: 1.0

24-Jul-2003
LOGIC GATE Inverter, 1x drive INV01






Fig. 50 Data sheet of an inverter